Method for measuring utilization of a power managed CPU

• US 7,788,511 B2
• Filed: 08/16/2007
• Issued: 08/31/2010
• Est. Priority Date: 08/16/2007
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Gary, Scott Paul
• Primary Examiner(s): Patel; Nitin C
• Application Number:
  US11/839,835
• Publication Number:
  US 20090048804A1
• Time in Patent Office: 1,111 Days
• Field of Search: 713/300, 702/176
• US Class Current: 713/300
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 11/3423 where the assessed time is active or idle time
• CPC Class Codes: G06F 9/30003 Arrangements for executing specific machine instructions
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

An extremely low overhead method calculates CPU load in the presence of both CPU idling and frequency scaling. The method measures time the CPU is idled while waiting for a wakeup. This invention uses a feature in current DSPs with the capability of delaying ISR processing on wake from IDLE. Using this mechanism it is possible to determine the time before IDLE, the time immediately following CPU wakeup, and then run the wakeup ISR. The delta time can be accumulated and compared to total time to determine true CPU load.

Claims

1. A method for computation of data processor utilization comprising the steps of:

accumulating total data processor execution time;

accumulating data processor idle time in a power reduced state; and

initially upon an interrupt of the data processor from the power reduced state performing the steps of;

deferring interrupt service from the power reduced state to read total data processing execution time,

reading data processor idle time;

accumulating data processor utilization;

totaling execution time and CPU idle time; and

thereafter upon any subsequent interrupt of the data processor from the power reduced state proceeding directly to service the interrupt.

2. The method of claim 1, wherein:

said step of accumulating total data processor execution time employs a hardware timer; and

said step of accumulating data processor idle time includes;

reading the hardware timer upon entry into the power reduced state,

reading the hardware timer upon exit from the power reduced state, and

calculating a data processor idle time as a difference between the time upon exit from the power reduced state and the time upon entry into the power reduced state.

3. The method of claim 2, wherein:

said step of calculating data processor utilization includes calculating 1 minus a ratio of data processor idle time to total data processor execution time.

4. The method of claim 1, wherein:

said step of accumulating total data processor execution time employs a data processor cycle counter; and

said step of accumulating data processor idle time includes;

reading the data processor cycle counter upon entry into the power reduced state,

reading the data processor cycle counter upon exit from the power reduced state, and

calculating a data processor idle count as a difference to the count upon exit from the power reduced state and the count upon entry into the power reduced state.

5. The method of claim 4, wherein:

said step of calculating data processor utilization includes calculating 1 minus a ratio of data processor idle count to total data processor execution count.

6. The method of claim 1, wherein:

said step of deferring interrupt from the power disabled state includes;

setting a global interrupt enable bit to disable,

upon receiving an interrupt if the global interrupt bit indicates enable, performing an interrupt service routine corresponding to the interrupt, and

upon receiving an interrupt if the global interrupt bit indicates disable, performing instructions next following an IDLE instruction causing the data processor to enter the power reduced state.

7. The method of claim 1, wherein:

said step of deferring interrupt from the power disabled state includes;

inserting code into each interrupt service which checks if the data processor was in a power reduced state,

performing the interrupt service routine if the data processor was not in a power reduced state, and

branching to a deferred interrupt routine and thereafter performing the interrupt service routine if the data processor was in a power reduced state.