Means and method for debugging

• US 7,788,535 B2
• Filed: 01/23/2006
• Issued: 08/31/2010
• Est. Priority Date: 01/28/2005
• Status: Expired due to Fees

• Current Assignee: NXP B.V. (NXP Semiconductors NV)
• Original Assignee: NXP B.V. (NXP Semiconductors NV)
• Inventors: Bussa, Nagaraju, Udupa, Narendranath, Karlapalem, Sainath
• Primary Examiner(s): Baderman, Scott T
• Assistant Examiner(s): PATEL, KAMINI B
• Application Number:
  US11/815,099
• Publication Number:
  US 20090217095A1
• Time in Patent Office: 1,681 Days
• Field of Search: 714/34
• US Class Current: 714/34
• CPC Class Codes: G06F 11/3648 using additional hardware

Abstract

A data processing system is provided comprising at least one processing unit (PU) for data processing and a debugger means (DM) for debugging the processing of the at least one processing unit (PU) based on a plurality of breakpoints. The debugger means (DM) comprises a first register (BAR) for storing a base address for one of the plurality of breakpoints, wherein the debugging means (DM) initiates the debugging of the processing of the at least one processing units (PU) based on the base address stored in the first breakpoint register, i.e. the base address register. A second breakpoint register (OR) is provided for storing an offset for obtaining subsequent breakpoints. A logic arithmetic unit (LAU) is provided for repetitively calculating a breakpoint condition based on the base address stored in the first breakpoint register and the offset stored in the second breakpoint register and for updating the base address stored in the first breakpoint register.

Claims

1. Data processing system, comprising:

at least one processing unit (PU) for processing an application; and

a debugger means (DM) for debugging the processing of the at least one processing unit (PU) based on a plurality of breakpoints, the debugger means (DM) comprising;

a first breakpoint register (BAR) for storing a base address for one of the plurality of breakpoints, wherein the debugging means (DM) initiates the debugging of the processing of the at least one processing units (PU) based on the address stored in the base address register (BAR),

a second breakpoint register (OR) for storing an offset from a base address for a breakpoint,

logic arithmetic unit (LAU) for repetitively detecting a breakpoint condition based on the base address stored in the first breakpoint register (BAR) and the offset stored in the second breakpoint register (OR) and for updating the base address stored in the first breakpoint register (BAR) accordingly.

2. Data processing system according to claim 1, further comprising a memory (MEM) acting as a FIFO with a pre-defined size being associated to the application processed by the at least one processing unit (PU), wherein the logic arithmetic unit (LAU) comprises an adder (ADD) for adding the content of the first and second breakpoint registers (BAR, OR), and a modulo operation unit (MOU) for performing a modulo operation on the output of the adder (ADD) with the pre-defined size of the FIFO, wherein the result of the modulo operation corresponds to the next base address to be updated in the first breakpoint register (BAR).

3. Method for debugging in a data processing system having at least one processing unit (PU) for processing an application, comprising the steps of:

debugging the processing of the at least one processing unit (PU) based on a plurality of breakpoints,

storing a base address for one of the plurality of breakpoints, wherein the debugging of the processing of the at least one processing units (PU) is initiated based on the stored base address,

storing an offset for a breakpoint,

repetitively detecting a subsequent breakpoint condition based on the stored base address and the stored offset and logic arithmetic operations, and

updating the stored base address accordingly.

4. Electronic device, comprising:

at least one processing unit (PU) for processing an application; and

a debugger means (DM) for debugging the processing of the at least one processing unit (PU) based on a plurality of breakpoints, the debugger means (DM) comprising;

a first breakpoint register (BAR) for storing a base address for one of the plurality of breakpoints, wherein the debugging means (DM) initiates the debugging of the processing of the at least one processing units (PU) based on the address stored in the base address register (BAR),

a second breakpoint register (OR) for storing an offset from a base address for a breakpoint,

logic arithmetic unit (LAU) for repetitively detecting a breakpoint condition based on the base address stored in the first breakpoint register (BAR) and the offset stored in the second breakpoint register (OR) and for updating the base address stored in the first breakpoint register (BAR) accordingly.