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Interleaver with linear feedback shift register

  • US 7,788,560 B2
  • Filed: 03/20/2008
  • Issued: 08/31/2010
  • Est. Priority Date: 05/18/2005
  • Status: Expired due to Fees
First Claim
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1. A circuit, comprising:

  • an address generator that comprises a linear feedback shift register and that provides an input address sequence and an output address sequence, the output address sequence having a pseudorandom mapping with respect to the input address sequence;

    a random access memory that has a data sequence input, an interleaved sequence output and an address input that receives the input address sequence and the output address sequence, the random access memory storing the data sequence input according to the input address sequence and the random access memory generating the interleaved sequence output according the output address sequence;

    wherein the address generator generates an input address sequence that comprises AG1 and the address generator generates an output address sequence that comprises (AG1+a constant) mod L, where L is a size of a data sequence received at the data sequence input.

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