Interleaver with linear feedback shift register
First Claim
1. A circuit, comprising:
- an address generator that comprises a linear feedback shift register and that provides an input address sequence and an output address sequence, the output address sequence having a pseudorandom mapping with respect to the input address sequence;
a random access memory that has a data sequence input, an interleaved sequence output and an address input that receives the input address sequence and the output address sequence, the random access memory storing the data sequence input according to the input address sequence and the random access memory generating the interleaved sequence output according the output address sequence;
wherein the address generator generates an input address sequence that comprises AG1 and the address generator generates an output address sequence that comprises (AG1+a constant) mod L, where L is a size of a data sequence received at the data sequence input.
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Abstract
An interleaver has an input multiplexer that receives a data sequence at an interleaver input and that separates the data sequence into multiple data sub-blocks. The interleaver has a linear feedback shift register that generates an input address sequence. The interleaver has adder circuits that generate output address sequences associated with each data sub-block. The interleaver has memory that stores the data sub-blocks at addresses controlled by the input address sequence. The memory reproduces each data sub-block in an interleaved sequence controlled by the associated output address sequence. The interleaver has an output multiplexer that assembles the interleaved sequences to provide an interleaver output.
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Citations
17 Claims
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1. A circuit, comprising:
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an address generator that comprises a linear feedback shift register and that provides an input address sequence and an output address sequence, the output address sequence having a pseudorandom mapping with respect to the input address sequence; a random access memory that has a data sequence input, an interleaved sequence output and an address input that receives the input address sequence and the output address sequence, the random access memory storing the data sequence input according to the input address sequence and the random access memory generating the interleaved sequence output according the output address sequence; wherein the address generator generates an input address sequence that comprises AG1 and the address generator generates an output address sequence that comprises (AG1+a constant) mod L, where L is a size of a data sequence received at the data sequence input. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A circuit, comprising:
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an address generator that comprises first and second linear feedback shift registers and that provides an input address sequence and an output address sequence, the output address sequence having a pseudorandom mapping with respect to the input address sequence; a random access memory that has a data sequence input, an interleaved sequence output, and an address input that receives the input address sequence and the output address sequence, the random access memory storing the data sequence input according to the input address sequence, and the random access memory generating the interleaved sequence output according the output address sequence; wherein the first linear feedback shift register implements a first primitive polynomial having a first polynomial degree, and the second linear feedback shift register implements a second primitive polynomial that is different than the first primitive polynomial, and the second primitive polynomial has a second polynomial degree that is the same as the first polynomial degree. - View Dependent Claims (9, 10, 11, 12)
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13. A method, comprising:
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providing a random access memory with a data sequence input and an interleaved sequence output; providing the random access memory with an address input that receives an input address sequence and an output address sequence, the random access memory storing the data sequence input according to the input address sequence, and the random access memory generating the interleaved sequence output according the output address sequence; generating the input address sequence and output address sequence with respective first and second linear feedback shift registers; providing the output address sequence with a pseudorandom mapping with respect to the input address sequence; implementing the first linear feedback shift register with a first primitive polynomial of a selected degree; and implementing the second linear feedback shift register with a second primitive polynomial that is different than the first primitive polynomial, the second primitive polynomial having the same degree as the selected degree. - View Dependent Claims (14, 15, 16, 17)
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Specification