Method and apparatus for using dual bit decisions to measure bit errors and event occurrences

• US 7,788,571 B2
• Filed: 12/10/2004
• Issued: 08/31/2010
• Est. Priority Date: 12/10/2003
• Status: Active Grant

• Current Assignee: Tektronix Incorporated (Fortive Corp.)
• Original Assignee: SyntheSys Research, Inc. (Fortive Corp.)
• Inventors: Verity, Robert L., Waschura, Thomas E.
• Primary Examiner(s): Baderman; Scott T
• Assistant Examiner(s): Ahmed; Enam
• Application Number:
  US11/009,381
• Publication Number:
  US 20070033448A1
• Time in Patent Office: 2,090 Days
• Field of Search: 714/795
• US Class Current: 714/795
• CPC Class Codes: G01R 31/3171 BER [Bit Error Rate] test
• CPC Class Codes: H04L 1/203 Details of error rate determination, e.g. BER, FER or WER
• CPC Class Codes: H04L 1/241 using pseudo-errors

Abstract

An apparatus and method for measuring errors and event occurrences in a multi-valued data stream by using a dual decision bit error rate tester is disclosed. The Bit error rate tester (BERT) includes a plurality of decision circuits operative to provide a respective bit decision output signal in response to an input signal. The bit decision output signal magnitude information of a signal under test as measured over a sample window period. A comparator circuit is coupled to each of the plurality of decision circuits, and is operative to provide an event occurrence signal in response to the bit decision output signals from each of the plurality of decision circuits. The BERT provides the ability to supply additional information and feedback about the behavior and performance of the targeted device or subsystem being tested and to perform error measurements in non-constrained data (i.e. live data).

Claims

1. A bit error rate tester circuit, comprising:

a plurality of decision circuits, each operative to provide a respective bit decision output signal corresponding to an input signal in response to a clock trigger signal representing a time offset sampling point within a sampling window period, each of the bit decision output signals being provided independent of one another and including non-constrained input signal magnitude information measured over the sampling window period; and

a comparator circuit, operative to provide an event occurrence signal in response to the bit decision output signals from each of the plurality of decision circuits.

2. The bit error rate tester circuit of claim 1, further including an error counter circuit operative to accumulate the number of error events within the sampling window period in response to the event occurrence signal.

3. The bit error rate tester circuit of claim 1, wherein the decision circuit includes:

a first comparator operative to generate an error signal in response to differences between the input signal and a first non-constrained threshold value;

a first delay element operative to provide a delayed clock trigger signal in response to a clock trigger signal; and

a first decision circuit, coupled to the first comparator, operative to generate a first decision output signal in response to the error signal and the delayed clock trigger signal.

4. The bit error rate tester circuit of claim 3, wherein the first non-constrained threshold value is a voltage magnitude.

5. The bit error rate tester circuit of claim 1, wherein the decision circuit includes:

a second comparator operative to generate a second error signal in response to differences between the input signal and a second non-constrained threshold value;

a second delay element operative to provide a second delayed clock trigger signal in response to a clock trigger signal; and

a second decision circuit, coupled to the first comparator, operative to generate a second decision output signal in response to the second error signal and the second delayed clock trigger signal.

6. The bit error rate tester circuit of claim 5, wherein the second non-constrained threshold value is a sampling time period.

7. The bit error rate tester circuit of claim 3, wherein the first delay element further includes a programmable device operative to adjust the amount of delay applied to the clock trigger signal in response to a control signal.

8. The bit error rate tester of claim 5, wherein the second delay element further includes a programmable device operative to adjust the amount of delay applied to the clock trigger signal in response to a control signal.

9. A dual decision circuit, comprising:

a first comparator operative to generate a first error signal in response to differences between an input signal and a first non-constrained threshold value;

a first delay element operative to provide a first delayed clock trigger signal representing a first time offset sampling point within a sampling window period in response to a clock trigger signal;

a first decision circuit, coupled to the first comparator, operative to generate a first decision output signal in response to the first error signal and the first delayed clock trigger signal;

a second comparator operative to generate a second error signal in response to differences between the input signal and a second non-constrained threshold value;

a second delay element operative to provide a second delayed clock trigger signal representing a second time offset sampling point within a sampling window period in response to a clock trigger signal; and

a second decision circuit, coupled to the second comparator, operative to generate a second decision output signal in response to the second error signal and the second delayed clock signal, wherein the first error signal and the second error signal are generated simultaneously and independently of one another.

10. The dual decision circuit of claim 9, wherein the first non-constrained threshold value is a voltage magnitude.

11. The dual decision circuit of claim 9, wherein the second non-constrained threshold value is a sampling time period.

12. The dual decision circuit of claim 9, wherein the first and second delay elements further include a programmable device operative to adjust the amount of delay applied to the clock trigger signal in response to a control signal.

13. The dual decision circuit of claim 9, wherein the first delay element is a fixed delay element, and wherein the circuit further includes a third delay element that is cascaded with the fixed delay element to provide the first delayed clock trigger signal.

14. The dual decision circuit of claim 13, wherein the third delay element is cascaded with the second delay element to provide the second delayed clock trigger signal in response to the clock trigger signal.