Method of manufacturing flexible semiconductor assemblies

• US 7,790,502 B2
• Filed: 12/10/2007
• Issued: 09/07/2010
• Est. Priority Date: 12/10/2007
• Status: Active Grant

• Current Assignee: Honeywell International Inc.
• Original Assignee: Honeywell International Inc.
• Inventors: Scheid, David R.
• Primary Examiner(s): Mulpuri; Savitri
• Assistant Examiner(s): CHOI, CALVIN Y
• Application Number:
  US11/953,541
• Publication Number:
  US 20090148983A1
• Time in Patent Office: 1,002 Days
• Field of Search: 438107-111, 438455-460, 257E21598-E21599
• US Class Current: 438/107
• CPC Class Codes: B81B 2201/0235 Accelerometers
• CPC Class Codes: B81B 7/0074 3D packaging, i.e. encapsulation containing one or several MEMS devices arranged in planes non-parallel to the mounting board
• CPC Class Codes: G01P 15/0802 Details
• CPC Class Codes: G01P 15/18 in two or more dimensions
• CPC Class Codes: H01L 21/67092 Apparatus for mechanical treatment or grinding or cutting, see the relevant groups in subclasses B24B or B28D
• CPC Class Codes: H01L 21/6836 Wafer tapes, e.g. grinding or dicing support tapes adhesive tapes in general C09J7/20
• CPC Class Codes: H01L 2221/68336 involving stretching of the auxiliary support post dicing
• CPC Class Codes: H01L 2224/03 Manufacturing methods
• CPC Class Codes: H01L 2224/11 Manufacturing methods
• CPC Class Codes: H01L 2224/94 at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 2224/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 23/5387 Flexible insulating substrates H01L23/5388 takes precedence
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 24/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 25/0655 the devices being arranged next to each other
• CPC Class Codes: H01L 25/16 the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01005 Boron [B]
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01013 Aluminum [Al]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19043 : being a resistor
• CPC Class Codes: H01L 2924/30105 : Capacitance

Abstract

A method for producing flexible semiconductor assemblies is described. For example, an integrated circuit package consisting of an X-Y axes sensor die and a Z-axis sensor die disposed at 90 degrees to each other may be formed by applying a flexible dielectric membrane to a semiconductor wafer, creating bending gaps between the sensor dice, singulating the IC package from the wafer, and bending the flexible dielectric membrane so that the sensor dice are disposed orthogonally to each other. This method eliminates the need to precisely position previously singulated sensor dice relative to each other in order to apply a flexible dielectric membrane for purposes of interconnecting the dice.

Claims

1. A method of fabricating an integrated circuit package from a wafer comprising a plurality of semiconductor dice, the wafer defining a first side and a second side, the method comprising:

attaching a flexible dielectric membrane to the first side of the wafer to form a wafer assembly, wherein the flexible dielectric membrane electrically interconnects a group of at least two adjacent semiconductor dice that are intended to form the integrated circuit package;

removing wafer material from the second side of the wafer to form one or more bending regions, wherein the wafer material is removed substantially to the depth of the flexible dielectric membrane, and further wherein the wafer material is removed between the at least two adjacent semiconductor dice within the group; and

singulating the integrated circuit package by removing the wafer material and flexible membrane material connecting the group of semiconductor dice to the wafer assembly.

2. The method of claim 1, wherein attaching the flexible dielectric membrane comprises laminating a sheet of flexible dielectric material to the wafer.

3. The method of claim 1, wherein attaching the flexible dielectric membrane comprises spinning at least one layer of a flexible dielectric material onto the wafer.

4. The method of claim 1, wherein the flexible dielectric membrane comprises a polyimide film.

5. The method of claim 1, wherein attaching the flexible dielectric membrane comprises:

creating vias through the flexible dielectric membrane down to the at least two adjacent semiconductor dice;

depositing a conductive material in the vias; and

forming conductive interconnection routes between the vias to create an interconnection interface.

6. The method of claim 5, further comprising:

attaching multiple sequential layers of a flexible dielectric material to form the flexible dielectric membrane, wherein the first sequential layer is attached to the wafer and each subsequent sequential layer is attached to the prior sequential layer; and

after each layer is attached, creating electrical interconnects by (i) creating vias through one or more of the flexible dielectric material layers, (ii) depositing a conductive material within the vias, and (iii) forming conductive interconnection routes between the vias to create an interconnection interface.

7. The method of claim 1, further comprising creating a pad layer at a section of the flexible dielectric membrane, wherein the pad layer overlays at least one of the plurality of semiconductor dice and is suitable for subsequent flip chip attachment or wire bond assembly.

8. The method of claim 1, wherein removing the wafer material comprises sawing the wafer assembly using a dicing saw, wherein the height of the dicing saw is set to remove substantially all of the wafer material between the at least two adjacent semiconductor dice within the group without substantially removing the flexible dielectric membrane.

9. The method of claim 1, wherein removing the wafer material comprises etching the wafer assembly to remove substantially all of the wafer material between the at least two adjacent semiconductor dice within the group without substantially removing the flexible dielectric membrane.

10. The method of claim 1, wherein singulating the integrated circuit package comprises sawing through the wafer assembly using a dicing saw.

11. The method of claim 1, wherein singulating the integrated circuit package comprises etching through the wafer assembly.

12. The method of claim 1, further comprising backgrinding the second side of the wafer to decrease the thickness of each of the at least two semiconductor dice.

13. The method of claim 1, further comprising backgrinding a side of the integrated circuit package opposite the flexible membrane to decrease the thickness of at least one of the semiconductor dice.

14. The method of claim 1, further comprising bending the flexible dielectric membrane at the one or more bending regions.

15. The method of claim 14, wherein bending the flexible dielectric membrane at the one or more bending regions comprises defining an angle between two adjacent dice within a range of 0 to 180 degrees.

16. The method of claim 1, wherein removing wafer material from the second side of the wafer to form one or more bending regions comprises forming a die gap region with a width between adjacent dice of between 10 microns and 100 microns.

17. A method of fabricating an integrated circuit package from a wafer comprising a plurality of semiconductor dice, the wafer defining a first side and a second side, the method comprising:

laminating a flexible dielectric sheet as a first dielectric layer to the first side of the wafer to form a wafer assembly;

using photolithography to create a first set of vias, wherein the first set of vias penetrates through the first dielectric layer to a group of at least two adjacent semiconductor dice that are intended to form the integrated circuit package;

depositing a first conductive material in the vias;

forming conductive interconnection routes between the vias to create a first interconnection interface;

depositing a second flexible dielectric layer;

using photolithography to create the second set of vias, wherein the second set of vias penetrates through the second dielectric layer to the interconnection interface of the first dielectric layer;

depositing a second conductive material in the second set of vias;

forming conductive interconnection routes between the second set of vias to create a second interconnection interface;

orienting the wafer assembly so that the second wafer side is face up;

using a dicing saw to remove wafer material from the second side of the wafer to form one or more bending regions, wherein the wafer material is removed substantially to the depth of the flexible dielectric membrane, and further wherein the material is removed between the at least two adjacent semiconductor dice within the group;

using a dicing saw to singulate the integrated circuit package by removing the wafer material and flexible membrane material connecting the group of semiconductor dice to the wafer assembly; and

bending the flexible dielectric membrane at the one or more bending regions.

18. The method of claim 17 wherein the first conductive material and the second conductive material are the same material.