Device and design structures for memory cells in a non-volatile random access memory and methods of fabricating such device structures

• US 7,790,524 B2
• Filed: 01/11/2008
• Issued: 09/07/2010
• Est. Priority Date: 01/11/2008
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Chatty, Kiran V., Abadeer, Wagdi W., Tonti, William R., Rankin, Jed H., Gauthier, Robert J. Jr., Shi, Yun
• Primary Examiner(s): Le; Thao X
• Assistant Examiner(s): Ullah; Elias
• Application Number:
  US11/972,949
• Publication Number:
  US 20090179251A1
• Time in Patent Office: 970 Days
• Field of Search: 438/266, 438/151, 257/E21.209
• US Class Current: 438/151
• CPC Class Codes: H01L 29/66825 with a floating gate H01L29/6684 takes precedence
• CPC Class Codes: H01L 29/7881 Programmable transistors with only two possible levels of programmation H01L29/7888 takes precedence

Abstract

Device and design structures for memory cells in a non-volatile random access memory (NVRAM) and methods for fabricating such device structures using complementary metal-oxide-semiconductor (CMOS) processes. The device structure, which is formed using a semiconductor-on-insulator (SOI) substrate, includes a floating gate electrode, a semiconductor body, and a control gate electrode separated from the semiconductor body by the floating gate electrode. The floating gate electrode, the control gate electrode, and the semiconductor body, which are both formed from the monocrystalline SOI layer of the SOI substrate, are respectively separated by dielectric layers. The dielectric layers may each be composed of thermal oxide layers grown on confronting sidewalls of the semiconductor body, the floating gate electrode, and the control gate electrode. An optional deposited dielectric material may fill any remaining gap between either pair of the thermal oxide layers.

Claims

1. A method of fabricating a device structure for a non-volatile random access memory from a semiconductor layer carried on an insulating layer, the method comprising:

forming first, second, and third semiconductor bodies from the semiconductor layer and with a juxtaposed relationship in which the second semiconductor body is disposed between the first and third semiconductor bodies;

doping the first semiconductor body to form a source and a drain;

forming a first dielectric layer between the first semiconductor body and the second semiconductor body;

forming a second dielectric layer between the second semiconductor body and the third semiconductor body;

after the first and second dielectric layers are formed, masking a first portion of the second semiconductor body and a first portion of the third semiconductor body; and

after the first portion of the second semiconductor body and the first portion of the third semiconductor body are masked, concurrently removing a second portion of the second semiconductor body and a second portion of the third semiconductor body with a selective etching process,

wherein the second semiconductor body and the third semiconductor body respectively define a floating gate electrode and a control gate electrode that cooperate to control carrier flow in a channel in the first semiconductor body between the source and the drain.

2. The method of claim 1 wherein the first semiconductor body includes a first sidewall and the second semiconductor body includes a second sidewall that confronts the first sidewall, and forming the first dielectric layer further comprises:

concurrently growing a first silicon dioxide layer on the first sidewall of the first semiconductor body and a second silicon dioxide on the second sidewall of the second semiconductor body with a thermal oxidation process.

3. The method of claim 2 wherein the first and second silicon dioxide layers are separated by a gap, and forming the first dielectric layer further comprises:

depositing a fill layer of a dielectric material to fill between the first and second silicon dioxide layers.

4. The method of claim 1 wherein the second semiconductor body includes a sidewall and the third semiconductor body includes a sidewall that confronts the sidewall of the second semiconductor body, and forming the second dielectric layer further comprises:

growing a first silicon dioxide layer on the sidewall of the second semiconductor body and a second silicon dioxide on the sidewall of the third semiconductor body with a thermal oxidation process.

5. The method of claim 4 wherein the first and second silicon dioxide layers are separated by a gap, and forming the first dielectric layer further comprises:

depositing a fill layer of a dielectric material to fill the gap between the first and second silicon dioxide layers; and

polishing the fill layer to planarize the dielectric material.

6. The method of claim 5 wherein the dielectric material of the fill layer is silicon dioxide.

7. The method of claim 4 wherein the first silicon dioxide layer and the second silicon dioxide layer are concurrently grown with the thermal oxidation process.

8. The method of claim 1 wherein the semiconductor layer is monocrystalline silicon, the first semiconductor body is formed concurrently with the second and third semiconductor bodies, and forming the first, second and third semiconductor bodies further comprises:

forming a hard mask on the monocrystalline silicon of the semiconductor layer;

patterning the hard mask with masked regions that are complimentary to the first, second, and third semiconductor bodies; and

concurrently removing unmasked portions of the layer of the monocrystalline silicon to form the first, second, and third semiconductor bodies.

9. The method of claim 1 wherein partially removing the second semiconductor body and the third semiconductor body further comprises:

partially masking the second and third semiconductor bodies with respective dielectric caps; and

concurrently removing unmasked portions of the second and third semiconductor bodies with an etching process that removes the unmasked portions selective to the dielectric caps to respectively define the control and floating gate electrodes.

10. The method of claim 9 further comprising:

forming a photoresist mask on the first semiconductor body to protect the first semiconductor body against the etching process when the unmasked portions of the second and third semiconductor bodies are removed.

11. The method of claim 1 wherein the control gate electrode has a sidewall, and the floating gate electrode has a sidewall that is aligned with the sidewall of the control gate electrode.

12. The method of claim 1 wherein the first dielectric layer is formed between the first semiconductor body and the second semiconductor body after the first and second semiconductor bodies are formed.

13. The method of claim 1 wherein the second dielectric layer is formed between the second semiconductor body and the third semiconductor body after the second and third semiconductor bodies are formed.

14. The method of claim 1 wherein the first dielectric layer is formed between the first semiconductor body and the second semiconductor body and the second dielectric layer is formed between the second semiconductor body and the third semiconductor body after the first, second, and third semiconductor bodies are formed.

15. The method of claim 1 wherein the partial removal of the second semiconductor body is concurrent with the partial removal of the third semiconductor body.

16. The method of claim 1 wherein the first, second, and third semiconductor bodies are concurrently formed from the semiconductor layer.