Structure and method to use low k stress liner to reduce parasitic capacitance

• US 7,790,540 B2
• Filed: 08/25/2006
• Issued: 09/07/2010
• Est. Priority Date: 08/25/2006
• Status: Expired due to Fees

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: International Business Machines Corporation
• Inventors: Li, Wai-Kin, Yang, Haining
• Primary Examiner(s): Coleman; W. David
• Assistant Examiner(s): CRAWFORD, LATANYA N
• Application Number:
  US11/467,186
• Publication Number:
  US 20080048271A1
• Time in Patent Office: 1,474 Days
• Field of Search: 438/299, 438/238, 438/780, 438/197, 438/199, 438/201, 257/E21.632
• US Class Current: 438/199
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823864 with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H01L 29/7843 the means being an applied insulating layer

Abstract

A low k stress liner, which replaces conventional stress liners in CMOS devices, is provided. In one embodiment, a compressive, low k stress liner is provided which can improve the hole mobility in pFET devices. UV exposure of this compressive, low k material results in changing the polarity of the low k stress liner from compressive to tensile. The use of such a tensile, low k stress liner improves electron mobility in nFET devices.

Claims

1. A method of fabricating a semiconductor structure comprising:

providing at least one field effect transistor (FET) on a surface of a semiconductor substrate, said at least one FET including at least a gate dielectric, an overlying gate electrode, a silicided source region located within the semiconductor substrate on one side of the FET and a silicided drain region located within the semiconductor substrate on another side of the FET;

forming a compressive stress liner on a portion of said semiconductor substrate and surrounding said at least one FET including atop both the silicided source region and the silicided drain region, wherein said compressive stress liner has a dielectric constant of less than 4.0; and

subjecting the compressive stress liner to UV treatment, said UV treatment converts said compressive stress liner into a tensile stress liner, said tensile stress liner is located at least atop the at least one FET and the entirety of the silicided source region and the silicided drain region, and wherein said compressive stress liner has a stress value of about 50 MPa or greater, and said tensile stress liner has a stress value of about 100 MPa to about 500 MPa.

2. The method of claim 1 wherein said forming said compressive stress liner comprises chemical vapor deposition of at least one of a silsesquioxane, a carbon doped oxide comprising atoms of Si, C, O and H, and a nitrogen and hydrogen doped silicon carbide comprising atoms of Si, C, N and H.

3. The method of claim 1 wherein said UV treatment comprises exposing said compressive stress liner to UV light having a wavelength ranging from about 180 to about 600 nm at an energy from about 10 to about 1000 mW/cm².

4. The method of claim 1 further comprising forming an ion diffusion barrier layer and an interlevel dielectric having at least one metallic contact on top of said tensile stress liner.

5. The method of claim 2 wherein said chemical vapor deposition is carried out at a temperature ranging from about 300°

to about 450°

C., a pressure ranging from about 0.5 to about 6 torr, and a plasma power level ranging from about 100 to about 1500 W.

6. A method of fabricating a semiconductor structure comprising:

providing at least one n-type field effect transistor (nFET) and at least one p-type field effect transistor (pFET) on a surface of a semiconductor substrate, said at least one nFET and said at least one pFET are separated by an isolation region located within said semiconductor substrate;

forming a compressive stress liner on a portion of said semiconductor substrate and surrounding said at least one nFET and said at least one pFET, wherein said compressive stress liner has a dielectric constant of less than 4.0;

forming a patterned UV blocking layer protecting a portion of said compressive stress liner located above and surrounding said at least one pFET, while leaving another portion of the compressive stress liner located above and surrounding said at least one nFET exposed;

subjecting the exposed portion of the compressive stress liner to UV treatment, said UV treatment converts said exposed portion of the compressive stress liner into a tensile stress portion, while maintaining a compressive stress portion underneath the patterned UV blocking layer; and

removing said patterned UV blocking layer, wherein an edge of the compressive stress portion is in contact with an edge of the tensile stress portion above the isolation region, and said compressive stress portion and said tensile stress portion form a single, continuous stress liner, and wherein said compressive stress liner has a stress value of about 50 MPa or greater, and said tensile stress liner has a stress value of about 100 MPa to about 500 MPa.

7. The method of claim 6 wherein said forming said compressive stress liner comprises chemical vapor deposition of at least one of a silsesquioxane, a carbon doped oxide comprising atoms of Si, C, O and H, and a nitrogen and hydrogen doped silicon carbide comprising atoms of Si, C, N and H.

8. The method of claim 6 wherein said UV treatment comprises exposing said compressive stress liner to UV light having a wavelength ranging from about 180 to about 600 nm at an energy from about 10 to about 1000 mW/cm².

9. The method of claim 6 further comprising forming an ion diffusion barrier layer and an interlevel dielectric having at least one metallic contact on top of said single, continuous stress liner.

10. The method of claim 7 wherein said chemical vapor deposition is carried out at a temperature ranging from about 300°

to about 450°

C., a pressure ranging from about 0.5 to about 6 torr, and a plasma power level ranging from about 100 to about 1500 W.