Structure and method to use low k stress liner to reduce parasitic capacitance
First Claim
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1. A method of fabricating a semiconductor structure comprising:
- providing at least one field effect transistor (FET) on a surface of a semiconductor substrate, said at least one FET including at least a gate dielectric, an overlying gate electrode, a silicided source region located within the semiconductor substrate on one side of the FET and a silicided drain region located within the semiconductor substrate on another side of the FET;
forming a compressive stress liner on a portion of said semiconductor substrate and surrounding said at least one FET including atop both the silicided source region and the silicided drain region, wherein said compressive stress liner has a dielectric constant of less than 4.0; and
subjecting the compressive stress liner to UV treatment, said UV treatment converts said compressive stress liner into a tensile stress liner, said tensile stress liner is located at least atop the at least one FET and the entirety of the silicided source region and the silicided drain region, and wherein said compressive stress liner has a stress value of about 50 MPa or greater, and said tensile stress liner has a stress value of about 100 MPa to about 500 MPa.
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Abstract
A low k stress liner, which replaces conventional stress liners in CMOS devices, is provided. In one embodiment, a compressive, low k stress liner is provided which can improve the hole mobility in pFET devices. UV exposure of this compressive, low k material results in changing the polarity of the low k stress liner from compressive to tensile. The use of such a tensile, low k stress liner improves electron mobility in nFET devices.
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Citations
10 Claims
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1. A method of fabricating a semiconductor structure comprising:
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providing at least one field effect transistor (FET) on a surface of a semiconductor substrate, said at least one FET including at least a gate dielectric, an overlying gate electrode, a silicided source region located within the semiconductor substrate on one side of the FET and a silicided drain region located within the semiconductor substrate on another side of the FET; forming a compressive stress liner on a portion of said semiconductor substrate and surrounding said at least one FET including atop both the silicided source region and the silicided drain region, wherein said compressive stress liner has a dielectric constant of less than 4.0; and subjecting the compressive stress liner to UV treatment, said UV treatment converts said compressive stress liner into a tensile stress liner, said tensile stress liner is located at least atop the at least one FET and the entirety of the silicided source region and the silicided drain region, and wherein said compressive stress liner has a stress value of about 50 MPa or greater, and said tensile stress liner has a stress value of about 100 MPa to about 500 MPa. - View Dependent Claims (2, 3, 4, 5)
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6. A method of fabricating a semiconductor structure comprising:
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providing at least one n-type field effect transistor (nFET) and at least one p-type field effect transistor (pFET) on a surface of a semiconductor substrate, said at least one nFET and said at least one pFET are separated by an isolation region located within said semiconductor substrate; forming a compressive stress liner on a portion of said semiconductor substrate and surrounding said at least one nFET and said at least one pFET, wherein said compressive stress liner has a dielectric constant of less than 4.0; forming a patterned UV blocking layer protecting a portion of said compressive stress liner located above and surrounding said at least one pFET, while leaving another portion of the compressive stress liner located above and surrounding said at least one nFET exposed; subjecting the exposed portion of the compressive stress liner to UV treatment, said UV treatment converts said exposed portion of the compressive stress liner into a tensile stress portion, while maintaining a compressive stress portion underneath the patterned UV blocking layer; and removing said patterned UV blocking layer, wherein an edge of the compressive stress portion is in contact with an edge of the tensile stress portion above the isolation region, and said compressive stress portion and said tensile stress portion form a single, continuous stress liner, and wherein said compressive stress liner has a stress value of about 50 MPa or greater, and said tensile stress liner has a stress value of about 100 MPa to about 500 MPa. - View Dependent Claims (7, 8, 9, 10)
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Specification