Device structures for a metal-oxide-semiconductor field effect transistor and methods of fabricating such device structures

• US 7,790,543 B2
• Filed: 01/11/2008
• Issued: 09/07/2010
• Est. Priority Date: 01/11/2008
• Status: Expired due to Fees

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: International Business Machines Corporation
• Inventors: Chatty, Kiran V., Abadeer, Wagdi W., Tonti, William R., Rankin, Jed H., Gauthier, Robert J. Jr., Shi, Yun
• Primary Examiner(s): Nguyen; Ha Tran T
• Assistant Examiner(s): BROWN, VALERIE N
• Application Number:
  US11/972,941
• Publication Number:
  US 20090179266A1
• Time in Patent Office: 970 Days
• Field of Search: 438/165
• US Class Current: 438/211
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

Device structures for a metal-oxide-semiconductor field effect transistor (MOSFET) that is suitable for operation at relatively high voltages and methods of forming same. The MOSFET, which is formed using a semiconductor-on-insulator (SOI) substrate, includes a channel in a semiconductor body that is self-aligned with a gate electrode. The gate electrode and semiconductor body, which are both formed from the monocrystalline SOI layer of the SOI substrate, are separated by a gap that is filled by a gate dielectric layer. The gate dielectric layer may be composed of thermal oxide layers grown on adjacent sidewalls of the semiconductor body and gate electrode, in combination with an optional deposited dielectric material that fills the remaining gap between the thermal oxide layers.

Claims

1. A method of fabricating a device structure on an insulating layer, the method comprising:

forming a first semiconductor body with a first sidewall that extends toward the insulating layer;

forming a second semiconductor body having a second sidewall that extends toward the insulating layer;

doping the first semiconductor body to form a source and a drain;

forming a gate dielectric layer extending to the insulating layer at a location between the first sidewall of the first semiconductor body and the second sidewall of the second semiconductor body; and

partially removing the second semiconductor body to define a gate electrode configured to control carrier flow in a channel between the source and the drain of the first semiconductor body,

wherein the gate dielectric layer is formed by concurrently growing a first silicon dioxide layer on the first sidewall of the first semiconductor body and a second silicon dioxide on the second sidewall of the second semiconductor body with a thermal oxidation process.

2. The method of claim 1 wherein the first and second silicon dioxide layers are separated by a gap, and forming the gate dielectric layer further comprises:

depositing a dielectric fill layer to fill between the gap between the first and second silicon dioxide layers.

3. The method of claim 2 wherein forming the gate dielectric layer further comprises:

masking the first and second silicon dioxide layers, the dielectric fill layer, and the channel with a photoresist mask orthogonally spanning the first and second semiconductor bodies; and

removing unmasked portions of the first and second silicon dioxide layers and the dielectric fill layer with an etching process.

4. The method of claim 3 further comprising:

using portions of the first and second silicon dioxide layers and the dielectric fill layer masked by the photoresist mask as an etch mask for partially removing unmasked portions of the second semiconductor body with another etching process.

5. The method of claim 1 wherein the first and second semiconductor bodies contain monocrystalline silicon, the first semiconductor body is formed concurrently with the semiconductor second body, and forming the first semiconductor body and the second semiconductor body further comprises:

forming a hard mask on a layer of the monocrystalline silicon in contact with the insulating layer;

patterning the hard mask with masked regions that are complimentary to the first and second semiconductor bodies; and

concurrently removing unmasked portions of the layer of the monocrystalline silicon to form the first and second semiconductor bodies.

7. The method of claim 1 wherein partially removing the second semiconductor body further comprises:

partially masking the second semiconductor body with a dielectric cap; and

removing unmasked portions of the second semiconductor body with an etching process that removes the unmasked portions selective to the dielectric cap to define the gate electrode.

8. The method of claim 7 further comprising:

forming a photoresist mask on the first semiconductor body to protect the first semiconductor body against the etching process when the unmasked portions of the second semiconductor body are removed.

9. The method of claim 1 wherein the first dielectric layer is formed between the first semiconductor body and the second semiconductor body after the first and second semiconductor bodies are formed.

6. A method of fabricating a device structure on an insulating layer, the method comprising:

forming a first semiconductor body with a first sidewall that extends toward the insulating layer;

forming a second semiconductor body having a second sidewall that extends toward the insulating layer;

doping the first semiconductor body to form a source and a drain;

forming a gate dielectric layer extending to the insulating layer at a location between the first sidewall of the first semiconductor body and the second sidewall of the second semiconductor body; and

partially removing the second semiconductor body to define a gate electrode configured to control carrier flow in a channel between the source and the drain of the first semiconductor body; and

non-concurrently forming another device structure on the insulating layer that includes a gate dielectric layer thinner than the gate dielectric layer of the device structure.