Method and apparatus for increase strain effect in a transistor channel

• US 7,790,558 B2
• Filed: 08/18/2006
• Issued: 09/07/2010
• Est. Priority Date: 01/16/2004
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Yang, Haining S., Zhu, Huilong
• Primary Examiner(s): Richards; N Drew
• Assistant Examiner(s): Garcia; Joannie A
• Application Number:
  US11/465,663
• Publication Number:
  US 20060281272A1
• Time in Patent Office: 1,481 Days
• Field of Search: 438/240, 438/253, 438/289, 438/303, 438/393, 438/525, 438/585, 438/586
• US Class Current: 438/286
• CPC Class Codes: H01L 29/6653 using the removal of at least part of spacer, e.g. disposable spacer
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/7842 means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate variation of the composition of the channel H01L29/1054

Abstract

Method of enhancing stress in a semiconductor device having a gate stack disposed on a substrate. The method utilizes depositing a nitride film along a surface of the substrate and the gate stack. The nitride film is thicker over a surface of the substrate and thinner over a portion of the gate stack.

Claims

1. A method of enhancing stress in a semiconductor device having a gate stack disposed on a substrate, comprising:

depositing a nitride film along a surface of the substrate and the gate stack having sidewalls,

wherein the deposited nitride film is thicker over a surface of the substrate and thinner over a portion of the gate stack and is thinner over a portion of the sidewalls of the gate stack than over the portion of the same gate stack.

2. The method of claim 1, further comprising forming a spacer adjacent only a lower portion of the gate stack.

3. The method of claim 2, wherein forming the spacer comprises reducing a size of the spacer.

4. The method of claim 3, wherein the reducing of the size of the spacer comprises reactive ion etching.

5. The method of claim 1, wherein the nitride film is a non-conformal nitride film.

6. The method of claim 1, wherein the depositing of the nitride film comprises a plasma enhanced vapor deposition process.

7. The method of claim 1, wherein the deposition of the nitride film provides enhanced stress within a transistor channel.

8. A method of enhancing stress in a semiconductor device, comprising:

depositing a layer of nitride film over a gate stack and a surface of a substrate such that the nitride film is thinner over a portion of vertical sides of the gate stack than over the same gate stack; and

removing the nitride film over the gate stack to provide enhanced stress in a transistor channel under the gate stack,

wherein a gate is about 60 nm wide, a spacer is about 50 rim wide, and the nitride film provides a stress of about 2.0 GPa, the enhanced stress in the transistor channel is greater than approximately 4.5×

10⁹ dynes/cm² at about 5 nm below a gate oxide, and

wherein, after the removing, a portion of the layer of nitride film remains on the surface of the substrate.

9. The method of claim 8, further comprising depositing a resist material on a surface of the nitride film over the substrate while leaving a surface of the nitride film proximate an upper portion of the gate stack exposed.

10. The method of claim 9, wherein the depositing of the resist material comprises depositing one of a spin-on material, an anti-reflection coating, an oxide film, and a low k material.

11. The method of claim 9, wherein the depositing of the resist material comprises depositing at least one of an oxide layer or a borophosphorosilicate glass on low spots and leaving high spots exposed.

12. The method of claim 8, wherein a gate is about 60 nm wide, a spacer is about 50 nm wide, and the nitride film provides a stress of about 2.0 GPa, the enhanced stress in the transistor channel is greater than approximately 4.5 ×

10⁹ dynes/cm² at about 5 nm below a gate oxide.

13. The method of claim 8, further comprising depositing a salicide gate region on top of the gate stack.

17. The method of claim 10, A method of enhancing stress in a semiconductor device, comprising:

depositing a layer of nitride film over a gate stack and a surface of a substrate such that the nitride film is thinner over a portion of vertical sides of the gate stack than over the same gate stack; and

removing the nitride film over the gate stack to provide enhanced stress in a transistor channel under the gate stack,

wherein a gate is about 60 nm wide, a spacer is about 50 nm wide, and the nitride film provides a stress of about 2.0 GPa, the enhanced stress in the transistor channel is greater than approximately 4.5×

10⁹ dynes/cm² at about 5 nm below a gate oxide, and

further comprising depositing a resist material on a surface of the nitride film over the substrate while leaving a surface of the nitride film proximate an upper portion of the gate stack exposed,

wherein the depositing of the resist material comprises depositing one of a spin-on material, an anti-reflection coating, an oxide film, and a low k material, and

further comprising forming spacers at a lower portion of the sidewalls of the gate stack.

18. The method of claim 17, wherein the forming of the spacers includes forming the spacers along substantially all of the sidewall and etching the spacers to form spacers at the lower portion of the sidewalls.

14. A method of enhancing stress in a semiconductor device, comprising:

depositing a layer of nitride film over a gate stack and a surface of a substrate;

removing the nitride film on the gate stack to provide enhanced stress in a transistor channel under the gate stack;

depositing a resist material on a surface of the nitride film over the substrate while leaving a surface of the nitride film proximate an upper portion of the gate stack exposed; and

removing an upper portion of the gate stack and the nitride film disposed thereon,

wherein a gate is about 60 nm wide, a spacer is about 50 nm wide, and the nitride film provides a stress of about 2.0 GPa, the enhanced stress in the transistor channel is greater than approximately 4.5×

10⁹ dynes/cm² at about 5 nm below a gate oxide.

15. The method of claim 14, wherein the removing of the upper portion of the gate stack and the nitride film disposed thereon comprises reactive ion etching.

16. The method of claim 14, wherein the removing of the upper portion of the gate stack and the nitride film disposed thereon comprises chemical mechanical polishing.

19. A method of enhancing stress in a semiconductor device, comprising:

depositing a layer of nitride film over a gate stack and a surface of a substrate;

removing the nitride film over the gate stack to provide enhanced stress in a transistor channel under the gate stack; and

forming sidewalls only at a lower portion of the gate stack,

wherein, after the depositing, the deposited nitride film is thicker over an upper surface of the gate stack and thinner over a portion of side surfaces of the same gate stack.

20. A method of enhancing stress in a semiconductor device, comprising:

depositing a layer of nitride film over a gate stack and a surface of a substrate such that the nitride film is thinner over a portion of side surfaces of the gate stack than over the same gate stack; and

removing the nitride film over the gate stack to provide enhanced stress in a transistor channel under the gate stack,

wherein for a semiconductor device having a gate about 60 nm wide, a spacer about 50 nm wide, and a nitride film stress of about 2.0 GPa, the enhanced stress in the transistor channel is greater than approximately 5.5×

10⁹ dynes/cm² at about 5 nm below a gate oxide, and

wherein, after the removing, a portion of the layer of nitride film remains on the surface of the substrate.

21. The method of claim 20, further comprising depositing a resist material on a surface of the nitride film over the substrate while leaving a surface of the nitride film proximate an upper portion of the gate stack exposed.

22. The method of claim 20, wherein the depositing of the resist material comprises depositing one of a spin-on material, an anti-reflection coating, an oxide film, and a low k material.

23. The method of claim 20, wherein the depositing of the resist material comprises depositing at least one of an oxide layer or a borophosphorosilicate glass on low spots and leaving high spots exposed.

24. A method of enhancing stress in a semiconductor device, comprising:

depositing a layer of nitride film over a gate stack and a surface of a substrate;

removing the nitride film on the gate stack to provide enhanced stress in a transistor channel under the gate stack;

depositing a resist material on a surface of the nitride film over the substrate while leaving a surface of the nitride film proximate an upper portion of the gate stack exposed; and

removing an upper portion of the gate stack and the nitride film disposed thereon,

wherein for a semiconductor device having a gate about 60 nm wide, a spacer about 50 nm wide, and a nitride film stress of about 2.0 GPa, the enhanced stress in the transistor channel is greater than approximately 5.5×

10⁹ dynes/cm² at about 5 nm below a gate oxide.

25. The method of claim 24, wherein the removing of the upper portion of the gate stack and the nitride film disposed thereon comprises reactive ion etching.

26. The method of claim 24, wherein the removing of the upper portion of the gate stack and the nitride film disposed thereon comprises chemical mechanical polishing.

27. A method of enhancing stress in a semiconductor device, comprising:

depositing a layer of nitride film over a gate stack and a surface of a substrate such that the nitride film is thinner over a portion of side surfaces of the gate stack than over the same gate stack; and

removing the nitride film over the gate stack to provide enhanced stress in a transistor channel under the gate stack.,

wherein for a semiconductor device having a gate about 60 nm wide, a spacer about 50 nm wide, and a nitride film stress of about 2.0 GPa, the enhanced stress in the transistor channel is greater than approximately 5.5×

10⁹ dynes/cm² at about 5 nm below a gate oxide, and

further comprising forming spacers at a lower portion of the sidewalls of the gate stack.

28. The method of claim 27, wherein the forming of the spacers includes forming the spacers along substantially all of the sidewall and etching the spacers to form spacers at the lower portion of the sidewalls.

29. A method of enhancing stress in a semiconductor device having a gate stack disposed on a substrate having a gate oxide formed on its upper surface, comprising:

forming spacers on sides of a polysilicon gate;

depositing a nitride film along a surface of the substrate and the gate stack such that the nitride film is thinner over a portion of the spacers than over the same gate stack;

applying a spin on material; and

removing a portion of the nitride film covering the gate stack and a top portion of the gate stack,

wherein the nitride film is thicker over a surface of the substrate and thinner over a portion of the same gate stack.