Formation of metal silicide layer over copper interconnect for reliability enhancement

• US 7,790,617 B2
• Filed: 11/12/2005
• Issued: 09/07/2010
• Est. Priority Date: 11/12/2005
• Status: Active Grant

• Current Assignee: Chartered Semiconductor Manufacturing Incorporated (Mamoura Diversified Global Holding PJSC)
• Original Assignee: Chartered Semiconductor Manufacturing Incorporated (Mamoura Diversified Global Holding PJSC)
• Inventors: Zhang, Hao, Gupta, Jyoti, Lim, Yeow Kheng, Seet, Chim Seng, Lu, Wei, Hsia, Liang Choo
• Primary Examiner(s): Bryant; Kiesha R
• Assistant Examiner(s): Yang; Minchul
• Application Number:
  US11/273,108
• Publication Number:
  US 20070111522A1
• Time in Patent Office: 1,760 Days
• Field of Search: 438/682, 438/683, 438/684, 438/687, 438/688, 257/E21.296, 257E21537-538
• US Class Current: 438/687
• CPC Class Codes: H01L 21/2855 by physical means, e.g. sputtering, evaporation H01L21/28518 - H01L21/28537 and H01L21/28568 take precedence
• CPC Class Codes: H01L 21/76831 in via holes or trenches, e.g. non-conductive sidewall liners
• CPC Class Codes: H01L 21/76849 the layer being positioned on top of the main fill metal
• CPC Class Codes: H01L 21/76883 Post-treatment or after-treatment of the conductive material

Abstract

A method of fabrication of a sputtered metal silicide layer over a copper interconnect. We form a dielectric layer over a conductive layer. We form an interconnect opening in the dielectric layer. We form a copper layer at least filling the interconnect opening. We planarize the copper layer to form a copper interconnect in the interconnect opening. The copper interconnect is over polished to form a depression. We form metal silicide layer over the copper interconnect using a low temperature sputtering process. We can form a cap layer over the metal silicide layer.

Claims

1. A method of forming an interconnect comprising:

providing an interconnect dielectric layer on a substrate of a semiconductor structure, the interconnect dielectric layer having a top surface;

providing an interconnect opening in the interconnect dielectric layer;

forming an interconnect in the interconnect opening with the top surface of the interconnect dielectric layer exposed, the interconnect having an interconnect top surface below the top surface of the interconnect dielectric layer to form a recess in the interconnect opening;

treating the interconnect top surface, wherein the treating comprises forming an oxide layer on the interconnect top surface in the opening; and

after treating the interconnect top surface, forming a blanket metal silicide layer on the exposed top surface of the interconnect dielectric layer and filling the recess using a non-reactive process, wherein the non-reactive process improves interconnect reliability.

2. The method of claim 1 which further includes planarizing the metal silicide layer to expose the top surface of the dielectric layer and to form a metal silicide cap in the recess.

3. The method of claim 1 wherein the low temperature process comprises a sputter process performed at a temperature between about 20 and 180 degrees C.

4. The method of claim 1 further comprises planarizing the metal silicide layer to form a metal silicide cap in the recess, the metal silicide cap has a thickness between about 100 and 200 angstroms, and the metal silicide layer is comprised of a material selected from the group consisting of WSi, CoSi, NiSi, and CuSi or a combination thereof.

5. The method of claim 1 wherein the dielectric layer comprises a low k dielectric material.

6. A method of forming an interconnect comprising:

forming a dielectric layer on a substrate, the dielectric layer serves as an interlevel dielectric in which an interconnect is formed, the dielectric layer is prepared with an interconnect opening;

depositing a conductive interconnect layer over the dielectric layer and at least filling the interconnect opening;

polishing the substrate, wherein polishing removes excess conductive interconnect material to expose a top surface of the dielectric layer and recesses the interconnect material to form a recess in the interconnect opening such that a top surface of the interconnect material is below the top surface of the dielectric layer;

treating a surface of the interconnect material by forming an oxide layer of the interconnect material on the top surface of the interconnect material in the interconnect opening;

after treating the surface, forming a blanket metal silicide layer on the exposed top surface of the dielectric layer and filling the recess using a low temperature process with temperatures at about 180 degrees C. or lower, wherein avoiding the use of a high-temperature chemical reactive process improves interconnect reliability; and

planarizing the metal silicide layer to expose the top surface of the dielectric layer and to form a metal silicide cap in the recess.

7. The method of claim 6 wherein:

the dielectric layer is comprised of TEOS or a low K material and has a thickness between 2000 and 6000 angstroms; and

the interconnect opening comprises a dual damascene opening.

8. The method of claim 6 wherein the conductive interconnect layer comprises copper (Cu) and depositing the conductive interconnect layer comprises:

forming a pore sealant selectively over the dielectric layer in the interconnect opening, the pore sealant is comprised of SiN, Parylene-N or Poly(p-xylyene);

forming a barrier layer over the dielectric layer, the barrier layer comprised of a material from the group consisting of TiN, TiSiN, Ta and TaN, or a combination thereof having a thickness between about 150 and 300 angstroms;

forming a Cu seed layer over the barrier layer, the Cu seed layer is a PVD Cu layer with a thickness between about 300 and 600 angstroms; and

forming the copper layer by an electroplating process over the seed layer.

9. The method of claim 6 wherein:

planarizing comprises chemical mechanical polishing; and

the recess is between about 100 and 200 angstroms below the top surface of the dielectric layer.

10. The method of claim 6 wherein the recess is between about 100 and 200 angstroms below the top surface of the dielectric layer.

11. The method of claim 6 wherein:

forming an oxide layer of the interconnect material comprises exposing the interconnect material to air; and

treating the surface of the interconnect material with a plasma process.

12. The method of claim 6 wherein the metal silicide layer is comprised of a material selected from the group consisting of WSi, CoSi, NiSi and CuSi, or a combination thereof.

13. The method of claim 6 wherein said metal silicide layer has a thickness between about 500 and 800 angstroms.

14. The method of claim 6 wherein the low temperature process is a sputtering process and comprises:

a target comprised substantially of metal and Si with a Si/Metal atomic ratio of between 2.7 and 2.9;

a DC power for sputtering is between 1000 to 3000 W;

Ar gas as sputtering gas;

a pressure less than 10 mtorr; and

a temperature between 20 and 180 degrees C.

15. The method of claim 6 wherein the metal silicide cap has a thickness between about 100 and 200 angstroms.

16. The method of claim 6 wherein:

the low temperature process comprises a sputter process at a temperature between about 20 and 180 degree C.; and

the metal silicide layer is comprised substantially of copper silicide.

17. A method of forming an interconnect comprising:

providing a substrate prepared with a dielectric layer in which an interconnect is formed;

forming an interconnect opening in the dielectric layer, the interconnect opening comprising a dual damascene opening;

forming a copper layer at least filling the interconnect opening, wherein

the copper layer is formed by an electroplating or electroless process;

planarizing the copper layer to expose a top surface of the dielectric layer and to form a copper interconnect in the interconnect opening, the copper interconnect having a top surface between about 100 and 300 angstroms below the top surface of the dielectric layer to form a recess in the interconnect opening;

treating a surface of the copper interconnect which include

forming a copper oxide layer on the surface of the copper interconnect in the interconnect opening, and

performing a plasma treatment on the surface of the interconnect;

after treating the surface of the interconnect, forming a metal silicide layer over the copper interconnect using a sputter process, wherein the metal silicide layer is formed using a sputter process at a temperature between about 20 and 180 degree C.,

the metal silicide layer is comprised of a material selected from the group consisting of WSi, CoSi, NiSi and CuSi, or a combination thereof;

planarizing said metal silicide layer to expose the top surface of the dielectric layer and to form a metal silicide cap in the recess.

18. The method of claim 17 which further includes forming a cap layer over the metal silicide cap and dielectric layer, the cap layer is comprised of a material selected from the group consisting of dielectric materials SiN, SiC(O) and SiC(N).

19. The method of claim 17 wherein forming the copper layer comprises:

forming a pore sealant selectively over the dielectric layer in the interconnect opening, the pore sealant is comprised of SiN, Parylene-N or Poly(p-xylyene);

forming a barrier layer over the dielectric layer, the barrier layer comprised of a material from the group consisting of TiN, TiSiN, Ta, TaN, or a combination thereof and has a thickness between about 150 and 200 angstroms;

forming a Cu seed layer over the barrier layer, the Cu seed layer is a PVD Cu layer with a thickness between about 50 and 500 angstroms; and

forming said copper layer by an electroplating process over the Cu seed layer.

20. The method of claim 19 wherein the sputtering process further comprising:

a target comprised substantially of metal and Si with a Si/W atomic ratio of between 2.7 and 2.9;

a DC power for sputtering is between 1000 to 3000 W;

Ar gas as sputtering gas; and

a pressure less than 10 mtorr.

21. The method of claim 17 wherein the metal silicide layer comprised substantially of copper silicide and is formed using a sputtering process further comprising:

a target comprised substantially of copper and Si with a Si/Cu atomic ratio of between 2.7 and 2.9;

a DC power for sputtering is between 1000 to 3000 W;

Ar gas as sputtering gas; and

a pressure less than 10 mtorr.

22. The method of claim 17 wherein the metal silicide cap has a thickness between 100 and 200 angstroms.

23. A method of forming an integrated circuit comprising:

providing a substrate prepared with a dielectric layer in which an interconnect is formed, the dielectric layer is prepared with an opening, the dielectric layer having a top surface;

filling the opening with a conductive layer, wherein the top surface of the dielectric layer is exposed and the conductive layer comprises a top surface below the top surface of the dielectric layer to form a recess in the opening;

forming an interconnect cap in the recess with the top surface of the dielectric layer exposed, the interconnect cap is formed using a non-reactive process, wherein the non-reactive process improves interconnect reliability; and

treating the top surface of the conductive layer prior to forming the interconnect cap, wherein the treating comprises,

forming an oxide layer on the top surface of the conductive layer in the opening, and

performing a plasma treatment on the top surface of the conductive layer.

24. The method of claim 23 wherein the interconnect cap comprises metal silicide cap.

25. The method of claim 23 wherein the conductive layer comprises copper.

26. The method of claim 25 wherein the interconnect cap comprises metal silicide cap.

27. The method of claim 23 wherein filling the opening comprises:

depositing a conductive layer comprising a conductive material; and

polishing the conductive layer to remove excess conductive material to form the recess in the opening and to expose the top surface of the dielectric layer.

28. The method of claim 23 wherein forming the interconnect cap comprises:

sputtering a cap layer on the substrate to cover the exposed top surface of the dielectric layer and filling the recess; and

polishing to remove excess material from the cap layer to expose the top surface of the dielectric layer and to form the interconnect cap in the recess.

29. The method of claim 28 wherein filling the opening comprises:

depositing a conductive layer comprising a conductive material; and

polishing the conductive layer to remove excess conductive material to form the recess in the opening and to expose the top surface of the dielectric layer.