Strained tri-channel layer for semiconductor-based electronic devices

• US 7,791,107 B2
• Filed: 06/16/2004
• Issued: 09/07/2010
• Est. Priority Date: 06/16/2004
• Status: Active Grant

• Current Assignee: Massachusetts Institute of Technology
• Original Assignee: Massachusetts Institute of Technology
• Inventors: Gupta, Saurabh, Lee, Minjoo Larry, Fitzgerald, Eugene A.
• Primary Examiner(s): SEFER, AHMED N
• Application Number:
  US10/869,463
• Publication Number:
  US 20050279992A1
• Time in Patent Office: 2,274 Days
• Field of Search: 257/19, 257/616, 257/24, 257/192, 438/590
• US Class Current: 257/192
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 29/1054 with a variation of the composition, e.g. channel with strained layer for increasing the mobility
• CPC Class Codes: H01L 29/4916 the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/4925 with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement with only a vertical doping structure or vertical doping variation H01L29/4916
• CPC Class Codes: H01L 29/495 the conductor material next to the insulator being a simple metal, e.g. W, Mo H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/4966 the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2 H01L29/4908, H01L29/4983 take precedence

Abstract

A semiconductor-based structure includes a substrate layer, a compressively strained semiconductor layer adjacent to the substrate layer to provide a channel for a component, and a tensilely strained semiconductor layer disposed between the substrate layer and the compressively strained semiconductor layer. A method for making an electronic device includes providing, on a strain-inducing substrate, a first tensilely strained layer, forming a compressively strained layer on the first tensilely strained layer, and forming a second tensilely strained layer on the compressively strained layer. The first and second tensilely strained layers can be formed of silicon, and the compressively strained layer can be formed of silicon and germanium.

Claims

1. A semiconductor-based structure, comprising:

a first tensilely strained layer consisting essentially of silicon;

a second tensilely strained layer consisting essentially of silicon;

a compressively strained layer forming a p-channel, and consisting essentially of silicon and germanium disposed between and in contact with the first and second tensilely strained layers, the first and second tensilely strained layers impeding diffusion of germanium out of the compressively strained layer;

a substrate in contact with the first tensilely strained layer that induces tensile strain into the first tensilely strained layer;

a gate disposed over the second tensilely strained layer to establish the p-channel;

a source region at a first side of the p-channel; and

a drain region at a second side of the p-channel.

2. The semiconductor-based structure of claim 1, wherein the first tensilely strained layer has a thickness selected to support an n-type channel.

3. The semiconductor-based structure of claim 2, wherein the thickness is in a range of about 5 nm to about 20 nm.

4. The semiconductor-based structure of claim 2, wherein the second tensilely strained layer has a thickness that is insufficient to support an effective n-type channel.

5. The semiconductor-based structure of claim 2, wherein the thickness of the second tensilely strained layer is in a range of about 1 nm to less than 7 nm.

6. The semiconductor-based structure of claim 1, wherein the first tensilely strained layer has a thickness greater than a diffusion length of germanium.

7. The semiconductor-based structure of claim 1, wherein the first tensilely strained layer has a thickness less than a thickness of the second tensilely strained layer.

8. The semiconductor-based structure of claim 7, wherein the thickness of the first tensilely strained layer is less than about 1.5 nm.

9. The semiconductor-based structure of claim 1, further comprising a NMOS component comprising a gate dielectric layer adjacent to the first tensilely strained layer, and a second gate in contact with the gate dielectric layer to form a n-type channel in at least one of the first and second tensilely strained layers.

10. The semiconductor-based structure of claim 9, wherein the n-type channel is formed at least mostly in the second tensilely strained layer.

11. The semiconductor-based structure of claim 9, wherein the gate dielectric layer is in contact with one of the second tensilely strained layer and the compressively strained layer.

12. The semiconductor-based structure of claim 11, further comprising a PMOS component comprising a second gate dielectric layer adjacent to the compressively strained layer, and a third gate in contact with the second gate dielectric layer to form a p-type channel at least mostly in the compressively strained layer.

13. The semiconductor-based structure of claim 1, wherein the substrate comprises silicon and germanium in contact with the first tensilely strained layer.

14. The semiconductor-based structure of claim 1, wherein the substrate comprises an oxide in contact with the first tensilely strained layer.

15. A semiconductor-based structure, comprising:

a substrate;

a compressively strained semiconductor layer adjacent to the substrate to provide a channel of a semiconductor component;

a tensilely strained semiconductor layer disposed between the substrate and the compressively strained semiconductor layer, and in contact with the compressively-strained semiconductor layer, the tensilely strained semiconductor layer impeding diffusion of a species out of the compressively strained semiconductor layer;

a gate disposed over the compressively strained layer to establish the channel;

a source region at a first side of the channel;

a drain region at a second side of the channel; and

a second tensilely strained layer consisting essentially of a semiconductor in contact with the compressively strained layer on an opposite side of the compressively strained layer relative to the tensilely strained layer;

wherein the substrate induces tensile strain into the tensilely strained semiconductor layer.

16. The semiconductor-based structure of claim 15, wherein the compressively strained semiconductor layer consists essentially of silicon and germanium, the tensilely strained semiconductor layer consists essentially of silicon, and the species is germanium.

17. The semiconductor-based structure of claim 15, further comprising at least one PMOS component that primarily utilizes the compressively strained layer for a p-type channel.

18. The semiconductor-based structure of claim 17, further comprising at least one NMOS component that primarily utilizes the tensilely strained layer for a n-type channel.

19. The semiconductor-based structure of claim 15, wherein, for a temperature in a range of about 300°

C. to about 1000°

C., the composition of the tensilely strained layer is selected to provide a diffusivity of Ge in the tensilely strained layer that is less than about 95% of a diffusivity of Ge in the compressively strained layer.

20. A method for making an electronic device, comprising:

providing, on a substrate, a first tensilely strained layer consisting essentially of silicon, wherein the substrate induces tensile strain into the first tensilely strained layer;

forming a compressively strained layer on the first tensilely strained layer, the compressively strained layer consisting essentially of silicon and germanium;

forming a second tensilely strained layer on the compressively strained layer, the second tensilely strained layer consisting essentially of silicon;

forming a gate over the second tensilely strained layer;

forming a source region at a first side of the compressively strained layer; and

forming a drain region at a second side of the compressively strained layer.

21. The method of claim 20, wherein the substrate comprises a layer in contact with the first tensilely strained layer, the layer consisting of one of an oxide and relaxed SiGe.

22. The method of claim 21, wherein providing the first tensilely strained layer comprises bonding the first tensilely strained layer to the substrate.