High performance stress-enhance MOSFET and method of manufacture

• US 7,791,144 B2
• Filed: 07/21/2009
• Issued: 09/07/2010
• Est. Priority Date: 04/28/2006
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Donaton, Ricardo A., Rim, Kern, Henson, William K., Chidambarrao, Dureseti
• Primary Examiner(s): Mandala; Victor A
• Assistant Examiner(s): STOWE, SCOTT C
• Application Number:
  US12/506,770
• Publication Number:
  US 20100013024A1
• Time in Patent Office: 413 Days
• Field of Search: 257/369, 257/E21.634, 257/E29.039, 257/E27.062, 438/154, 438/199, 438/229, 438/218, 438/275, 438/299, 438/303, 438/938
• US Class Current: 257/369
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823814 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 29/1054 with a variation of the composition, e.g. channel with strained layer for increasing the mobility
• CPC Class Codes: H01L 29/6653 using the removal of at least part of spacer, e.g. disposable spacer
• CPC Class Codes: H01L 29/66636 with source or drain recessed by etching or first recessed by etching and then refilled
• CPC Class Codes: H01L 29/7843 the means being an applied insulating layer
• CPC Class Codes: H01L 29/7848 the means being located in the source/drain region, e.g. SiGe source and drain
• CPC Class Codes: Y10S 438/938 Lattice strain control or utilization

Abstract

The invention relates to a semiconductor structure and method of manufacturing and more particularly to a CMOS device with a stress inducing material embedded in both gates and also in the source/drain of the PFET and varying thickness of the PFET and NFET channel. In one embodiment, the structure enhances the device performance by varying the thickness of the top Silicon layer respective to the NFET or the PFET.

Claims

1. A method of manufacturing a semiconductor structure, comprising:

forming a stress inducing layer on a substrate in an NFET region and a PFET region;

forming a top layer over the stress inducing layer in the NFET region and the PFET region, the top layer being of a different thickness in the NFET region and the PFET region;

etching trenches into sides of the PFET region and the NFET region, the etching of the trenches creating a tensile stress in the NFET region and a reduced tensile stress in the PFET region; and

filing the trenches with a first material for the NFET region and a second material for the PFET region, the second material creating a compressive stress in the PFET region.

2. The method of claim 1, wherein the top layer of the PFET region is formed by depositing or growing more material on the PFET region, forming a thicker top layer in the PFET region, while protecting the NFET region.

3. The method of claim 2, wherein the thicker top layer in the PFET region is of a same material as the top layer in the NFET region, the thicker layer in the PFET region substantially reduces the stress in the channel imposed by the stress inducing layer upon etching of the trenches in the PFET region.

4. The method of claim 1, wherein the stress inducing material and the second material is a silicon germanium composite.

5. The method of claim 4, wherein the tip layer and the first material is silicon.

6. The method of claim 1, wherein a thickness of the top layer differ in the range of 50 to 500 Å

.

7. The method of claim 1, wherein the second material is a silicon germanium composite.

8. A semiconductor structure comprising a PFET device and an NFET device, the PFET device and the NFET device having a layered structure of the same materials in the channel region, a top layer of the same materials in the PFET channel region is thicker than a top layer of the NFET channel region, and trenches of the PFET channel region and the NFET channel region are different, wherein the top layer in the PFET channel region reduces a tensile stress generated by a stress inducing underlying layer upon trench etching, compared to that of the NFET channel region.

9. The structure of claim 8, wherein stress inducing layer and the trenches of the PFET channel region is a silicon germanium composite.

10. A semiconductor structure, comprising:

a layered structure with an underlying stress inducing material, in a P-type field-effect-transistor (PFET) channel region and a n-type field effect-transistor (NFET) channel region formed simultaneously;

a layer over the underlying stress inducing material of the PFET channel region while protecting the NFET channel region;

an island in the NFET channel region and the PFET channel region, creating a higher resultant stress component in the NFET channel region; and

a stress inducing material in etched portions of the PFET channel region creating an opposite stress component in the PFET channel region than in the NFET channel region.

11. The structure of claim 10, wherein the layered structured with an underlying stress inducing material includes a top layer of Si and an underlying layer of SiGe, wherein the top layer of Si is of a different thickness respective to the NFET or PFET channel regions.

12. The structure of claim 10, wherein the PFET channel region is thicker than the NFET channel region.

13. The structure of claim 10, wherein the PFET channel region has a top layer thicker than the NFET channel region.

14. The structure of claim 10, wherein the layered structure with an underlying stress inducing material includes a top layer of Si and an underlying layer of SiGe, wherein the top layer of Si in the PFET channel region is thicker than the top layer of Si in the NFET channel region.

15. The structure of claim 14, wherein the germanium content of the SiGe is approximate from 20% and 30%.

16. The structure of claim 14, wherein a thickness of the top layer of Si in the PFET channel region is approximately 400 Å

.

17. The structure of claim 10, wherein the PFET channel region includes an Si layer having a thickness which substantially reduces tensile stress in the PFET channel region.

18. The structure of claim 17, wherein the stress inducing material in the etched portions of the PFET channel region provide compressive forces in the PFET channel region.