On silicon interconnect capacitance extraction

• US 7,791,357 B2
• Filed: 12/19/2005
• Issued: 09/07/2010
• Est. Priority Date: 12/23/2004
• Status: Expired due to Fees

• Current Assignee: NXP B.V. (NXP Semiconductors NV)
• Original Assignee: NXP B.V. (NXP Semiconductors NV)
• Inventors: Wieling, Jean, Pavithran, Praveen, Veendrick, Hendricus Joseph, Pelgrom, Marcel
• Primary Examiner(s): Dole; Timothy J
• Assistant Examiner(s): Baldridge; Benjamin M
• Application Number:
  US11/722,629
• Publication Number:
  US 20080143348A1
• Time in Patent Office: 1,723 Days
• Field of Search: 324/681
• US Class Current: 324/681
• CPC Class Codes: G01R 27/2605 Measuring capacitance capacitive sensors G01D5/24
• CPC Class Codes: G01R 31/2853 Electrical testing of internal connections or -isolation, e.g. latch-up or chip-to-lead connections G01R31/31717 takes precedence; test of chip-to-PCB or lead-to-PCB connections G01R31/66

Abstract

The present invention relates to a on-chip circuit for on silicon interconnect capacitance (Cx) extraction that is self compensated for process variations in the integrated transistors. The circuit (10) comprises signal generation means (20) for generating a periodical pulse signal connected to first and to second signal delaying means (31, 32) for respective delaying said pulse signal, wherein said second signal delaying means (32) are configured to have a delay affected by said interconnect capacitance (Cx); a logical XOR gate (35) for connecting respective first and said second delay signals of said respective first and second delay means (31, 32), said logical XOR gate (35) being connected to signal integrating means (40); and said signal integrating means (40) being connected to analog to digital converting means (50). Whilst the error in conventional uncompensated systems, like delay line only, the error can be up to 30%, in the circuit according to the invention, the error due to process variations in the front-end is about 2%. Further, an output is provided in a digital format and thus, can be measured quickly with simple external hardware. Furthermore, the pulse signal frequency can be used as a monitor to measure process variations in the front-end. Moreover, since the circuit (10) is remarkably accurate and very easy to measure, it is the best choice as a process monitor for every chip fabricated in the future.

Claims

1. A circuit for interconnect capacitance measurement integrated on a semiconductor chip comprising:

signal generation means for generating a periodical pulse signal connected to an input of a first signal delaying means and to an input of a second signal delaying means, wherein each of the first and second signal delaying means delays said pulse signal, and wherein said second signal delaying means is configured to have a delay affected by said interconnect capacitance;

a logical exclusive or (XOR) gate means for receiving the first and second delay signals from the outputs of said first and second delay means, the output of said logical XOR gate means being connected to the input of signal integrating means; and

the output of said signal integrating means being connected to analog to digital converting means.

2. The circuit according to claim 1 further comprising frequency counting means connected to said signal generation means.

3. The circuit according to claim 1, wherein said signal generation means comprises a logical NAND gate means and a feed-back loop with a first even number of consecutive connected logical gate elements.

4. The circuit according to claim 3, wherein each of said logical gate elements is a logical inverter gate means.

5. The circuit according to claim 1, wherein each of said first and second delay means comprises a second even number of consecutive connected logical gate elements, said logical gate elements of said second delay means being loaded at respective outputs with said capacitance.

6. The circuit according to claim 5, wherein each of said first and second delay means further comprise an additional logical gate element interconnected between said respective delay means and said logical XOR gate means.

7. The circuit according to claim 1, wherein said circuit is integrated on a semiconductor chip containing other integrated circuitry.

8. A semiconductor chip comprising a circuit according to claim 1.

9. The circuit according to claim 1, wherein at least one of said first signal delaying means and said second signal delaying means of said circuit is not a ring oscillator.

10. The circuit according to claim 1, wherein neither said first signal delaying means nor said second signal delaying means of said circuit is a ring oscillator.

11. A method for extraction of interconnect capacitance in a semiconductor chip, comprising the steps of:

generating a periodic pulse signal;

delaying said pulse signal by a first and by a second delay means, wherein a delay of said second delay means is affected by said capacitance;

logically combining said respective first delayed pulse signal and second delayed pulse signal by a logical exclusive or (XOR) function for deriving a differential pulse signal;

integrating said differential pulse signal; and

converting said integrated differential pulse signal into a digital output signal.

12. The method according to claim 11, said method further comprising the step of counting a pulse frequency of said pulse signal of said generating step.

13. The method according to claim 11, wherein at least one of said first signal delaying means and said second signal delaying means of said circuit is not a ring oscillator.

14. The method according to claim 11, wherein neither said first signal delaying means nor said second signal delaying means of said circuit is a ring oscillator.