Clock distribution techniques for channels

• US 7,791,370 B1
• Filed: 05/21/2009
• Issued: 09/07/2010
• Est. Priority Date: 05/21/2009
• Status: Active Grant

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Altera Corporation (Intel Corporation)
• Inventors: Tran, Thungoc M., Wong, Wilson, Shumarayev, Sergey, Hoang, Tim Tri
• Primary Examiner(s): Tran; Anh Q
• Application Number:
  US12/470,455
• Time in Patent Office: 474 Days
• Field of Search: None
• US Class Current: 326/38
• CPC Class Codes: G06F 1/10 Distribution of clock signals , e.g. skew

Abstract

A circuit includes a first area, a second area, and a third area. The second area includes a locked loop circuit that generates a clock signal. The locked loop circuit receives a supply voltage that is isolated from noise generated in the first area. The third area includes multiple quads of channels and a clock line coupled to route at least one clock signal generated in the second area to the channels in each of the quads. The third area is separate from the second area in the circuit.

Claims

1. A circuit comprising:

a first area;

a second area comprising a first locked loop circuit that generates a first clock signal, the first locked loop circuit receiving a supply voltage that is isolated from noise generated in the first area; and

a third area comprising multiple quads of channels and a clock line coupled to route at least one clock signal generated in the second area to the channels in each of the quads, wherein the third area is separate from the second area in the circuit.

2. The circuit defined in claim 1 wherein the third area further comprises a second locked loop circuit that generates a second clock signal in response to the first clock signal received from the clock line, and a clock routing network coupled to route the second clock signal to transmitters in each of the quads.

3. The circuit defined in claim 2 wherein the clock line comprises conductors and bi-directional buffer circuits that are configurable to serially couple the conductors together, and each of the bi-directional buffer circuits is configurable to be turned off in response to at least one enable signal to electrically isolate two of the conductors into separate segments.

4. The circuit defined in claim 3 wherein the second area further comprises a third locked loop circuit that generates a third clock signal and a fourth locked loop circuit that generates a fourth clock signal, and wherein the bi-directional buffer circuits are configurable to divide the clock line into at least three segments so that each of the segments routes one of the first, the third, and the fourth clock signals to receivers in at least one of the quads.

5. The circuit defined in claim 1 wherein each of the quads comprises regular channels and clock multiplier unit channels, and each of the regular channels and the clock multiplier unit channels is configured to transmit and receive data through pins.

6. The circuit defined in claim 5 wherein the third area comprises at least 4 quads, and each of the quads comprises 6 channels that are configurable to transmit and receive data.

7. The circuit defined in claim 1 wherein the circuit is a field programmable gate array integrated circuit, and the first area comprises programmable logic circuits.

8. The circuit defined in claim 2 wherein the clock routing network comprises first multiplexers configurable to route the second clock signal to transmitters in at least two of the quads, and second multiplexers configurable to route the second clock signal to transmitters in at least two of the quads.

9. The circuit defined in claim 8 wherein the third area further comprises a third locked loop circuit that generates a third clock signal in response to a clock signal received from the clock line, the first multiplexers are configurable to route the third clock signal to transmitters in at least three of the quads, and the second multiplexers are configurable to route the third clock signal to transmitters in at least one of the quads.

10. The circuit defined in claim 2 wherein the first locked loop circuit is a first phase-locked loop, and the second locked loop circuit is a second phase-locked loop.

11. An integrated circuit comprising:

a first area;

a second area comprising a first locked loop circuit that generates a first clock signal, and a second locked loop circuit that generates a second clock signal, the first and the second locked loop circuits receiving a supply voltage that is isolated from noise generated in the first area; and

a third area comprising groups of channels and a clock line that comprises a first segment coupled to route the first clock signal to the channels in at least one of the groups, a second segment coupled to route the second clock signal to the channels in at least one of the groups, and a buffer coupled to the first and the second segments of the clock line that is configurable to isolate the first and the second segments from each other.

12. The integrated circuit defined in claim 11 wherein the third area further comprises a third locked loop circuit that generates a third clock signal in response to a clock signal received from the clock line, and a clock routing network configurable to route the third clock signal to transmitters in the channels in each of the groups.

13. The integrated circuit defined in claim 12 wherein the third area further comprises a fourth locked loop circuit that generates a fourth clock signal in response to a clock signal received from the clock line and a fifth locked loop circuit that generates a fifth clock signal in response to a clock signal received from the clock line, and wherein the clock routing network is configurable to route the fourth and the fifth clock signals to transmitters in the channels in each of the groups.

14. The integrated circuit defined in claim 11 wherein the first segment of the clock line comprises a first conductor, the second segment of the clock line comprises a second conductor, and the buffer is a bi-directional buffer circuit coupled to the first and the second conductors.

15. The integrated circuit defined in claim 11 wherein the second area further comprises a third locked loop circuit that generates a third clock signal and receives the supply voltage, and wherein the clock line further comprises a third segment coupled to route the third clock signal to the channels in at least one of the groups.

16. The integrated circuit defined in claim 11 wherein each of the groups of channels comprises at least 2 regular channels and at least 2 clock multiplier unit channels, each of the regular channels and the clock multiplier unit channels in the groups are configured to transmit and receive data through pins, and the third area comprises at least 4 of the groups.

17. The integrated circuit defined in claim 11 wherein the second area and the third area are separated by a physical coding sub-layer.

18. The integrated circuit defined in claim 13 wherein the first and the second locked loop circuits are coupled to receive reference clock signals through input pins, and wherein the clock line is configurable to route the first and the second clock signals to the third, the fourth, and the fifth locked loop circuits.

19. The integrated circuit defined in claim 13 wherein the integrated circuit is a field programmable gate array integrated circuit, and the first area comprises programmable logic circuits.

20. A method for routing clock signals to channels, the method comprising:

generating a first clock signal in a first area of a circuit in response to a first input reference clock signal and a supply voltage that is isolated from noise generated in a second area of the circuit;

generating a second clock signal in the first area of the circuit in response to a second input reference clock signal and the supply voltage;

routing the first clock signal through a first segment of a clock line to channels in a first quad in a third area of the circuit; and

routing the second clock signal through a second segment of the clock line to channels in a second quad in the third area.

21. The method defined in claim 20 further comprising:

generating a third clock signal in the first area of the circuit in response to a third input reference clock signal and the supply voltage; and

routing the third clock signal through a third segment of the clock line to channels in a third quad in the third area.

22. The method defined in claim 21 further comprising:

generating a fourth clock signal in the third area in response to one of the first, the second, and the third clock signals;

generating a fifth clock signal in the third area in response to one of the first, the second, and the third clock signals;

routing the fourth clock signal to channels in at least one of the first, the second, and the third quads; and

routing the fifth clock signal to channels in at least one of the first, the second, and the third quads.

23. A circuit comprising:

means for generating a first clock signal in a first area of a circuit in response to a first input reference clock signal and a supply voltage that is isolated from noise generated in a second area of the circuit;

means for generating a second clock signal in the first area of the circuit in response to a second input reference clock signal and the supply voltage;

means for routing the first clock signal through a first segment of a clock line to channels in a first group of channels in a third area of the circuit;

means for routing the second clock signal through a second segment of the clock line to channels in a second group of channels in the third area; and

means for isolating the first segment of the clock line from the second segment of the clock line.