Fine-resolution edge-extending pulse width modulator

• US 7,791,387 B1
• Filed: 08/14/2005
• Issued: 09/07/2010
• Est. Priority Date: 08/14/2005
• Status: Active Grant

• Current Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Original Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Inventors: Wong, Hee
• Primary Examiner(s): Donovan; Lincoln
• Assistant Examiner(s): Almo; Khareem E
• Application Number:
  US11/204,285
• Time in Patent Office: 1,850 Days
• Field of Search: None
• US Class Current: 327/172
• CPC Class Codes: H03K 7/08 Duration or width modulation ; Duty cycle modulation
• CPC Class Codes: H03M 1/0639 using dither, e.g. using triangular or sawtooth waveforms for increasing resolution H03M1/201
• CPC Class Codes: H03M 1/68 with conversions of different sensitivity, i.e. one conversion relating to the more significant digital bits and another conversion to the less significant bits
• CPC Class Codes: H03M 1/822 using pulse width modulation

Abstract

Fine resolution pulse width modulation is achieved through feed-forward edge extending logic. A ring-oscillator produces phase-shifted versions of a system clock and two latches operate in parallel with the system clock output from the multiplexer clocking a first latch and a selected phase-shifted version of the system clock from the multiplexer clocking the second latch. The first latch receives a coarse output pulse equal to a selected number of clock periods as an input, while the second latch receives the output of the first latch as an input. A logic gate combines outputs from the latches to produce the output pulse having a trailing edge extended by a selected number of phase divisions.

Claims

1. A digital pulse width modulator comprising:

a system clock signal generator; and

a feed-forward logic circuit coupled to the system clock signal generator, wherein the circuit receives a system clock signal, produces a pulse having a leading edge at one of a plurality of phase offsets relative to the system clock signal based on a state counter value, and extends a trailing edge of the pulse following the duration of system clock periods by a predetermined number of fractional portions of the system clock period, wherein the pulse has a duration at least equal to a selected number of periods of the system clock signal, wherein the leading and trailing edges are separated by the selected number of system clock periods plus the selected number of fractional portions of the system clock period, wherein the plurality of phase offsets are used to perform a fine adjustment to an output of the pulse width modulator.

2. The digital pulse width modulator according to claim 1, wherein the feed-forward logic further comprises a ring-oscillator generating a number of phase-shifted versions of a system clock.

3. The digital pulse width modulator according to claim 2, wherein the feed forward logic further comprises at least one latch clocked by one of the phase-shifted versions of the system clock, the latch extending the trailing edge of the pulse.

4. The digital pulse width modulator according to claim 3, wherein the at least one latch further comprises:

a second latch operating in parallel with the latch and clocked by the system clock; and

a logic gate combining outputs of the latch and the second latch to form the pulse.

5. The digital pulse width modulator according to claim 4, wherein an input to the latch receives an output from the second latch.

6. The digital pulse width modulator according to claim 4, further comprising a multiplexer that receives the phase-shifted versions of the system clock and outputs the system clock on the first output and the one phase-shifted version of the system clock on the second output.

7. An integrated circuit including the digital pulse width modulator according to claim 4, the integrated circuit further comprising:

an input receiving an external timing reference; and

bus interface logic receiving external control signals.

8. A method of digital pulse width modulation comprising:

receiving a system clock signal;

utilizing feed-forward logic, producing a pulse having a leading edge at one of a plurality of phase offsets relative to the system clock signal based on a state counter value and a duration at least equal to a selected number of periods of the system clock signal and extending a trailing edge of the pulse following the duration of the selected number of system clock periods by a selected number of fractional portions of the system clock period so that the leading and trailing edges are separated by the selected number of system clock periods plus the selected number of fractional portions of the system clock period, wherein the plurality of phase offsets are used to perform a fine adjustment to a modulated output signal that includes the pulse.

9. The method according to claim 8, further comprising:

generating a number of phase-shifted versions of a system clock.

10. The method according to claim 9, further comprising:

clocking a latch extending the trailing edge of the pulse by one of the phase-shifted versions of the system clock.

11. The method according to claim 10, further comprising:

operating a second latch in parallel with the first latch;

clocking the second latch by the system clock; and

combining outputs of the latch and the second latch to form the pulse.

12. The method according to claim 11, furthering comprising:

receiving, at an input to the latch, an output from the second latch.

13. The method according to claim 11, further comprising:

multiplexing the phase-shifted versions of the system clock to output the system clock on a first output and the one phase-shifted version of the system clock on a second output.

14. A digital pulse width modulator comprising:

a ring-oscillator receiving a system clock and producing a plurality of phase-shifted versions of the system clock;

a multiplexer receiving the system clock and the plurality of phase-shifted versions of the system clock, the multiplexer outputting the system clock on a first output and one of the phase-shifted versions of the system clock on a second output; and

first and second latches, wherein the first output of the multiplexer is received as an input to the first latch, and the second output of the multiplexer is received as an input to the second latch, the first latch clocked by the first output of the multiplexer and the second latch clocked by the second output of the multiplexer, the second latch selectively extending a trailing edge of a pulse from the first latch by a selected number of phase divisions of a period of the system clock based upon a state counter value, wherein the second latch performs a fine adjustment to the output of the pulse width modulator.

15. The digital pulse width modulator according to claim 14, further comprising:

a logic gate combining outputs of the first and second latches to produce the pulse.

16. The digital pulse width modulator according to claim 15, further comprising:

a programmable state counter providing the state counter value for controlling the number of phase divisions by which the trailing edge is extended.

17. The digital pulse width modulator according to claim 16, wherein the second latch receives, at a second input thereof, the output of the first latch.

18. The digital pulse width modulator according to claim 17, further comprising:

a pulse width modulator receiving a signal from the state counter and producing an output pulse having a duration equal to a selected number of system clock periods, wherein the output pulse is received at a second input to the first latch.

19. The digital pulse width modulator according to claim 17, wherein the multiplexer passes through the system clock to the first output from which the first latch is clocked.

20. An integrated circuit including the digital pulse width modulator according to claim 17, the integrated circuit further comprising:

an input receiving an external timing reference; and

bus interface logic receiving external control signals.