Mixed-mode PLL

• US 7,791,417 B2
• Filed: 01/07/2009
• Issued: 09/07/2010
• Est. Priority Date: 01/07/2008
• Status: Active Grant

• Current Assignee: MediaTek, Inc.
• Original Assignee: MediaTek, Inc.
• Inventors: Zhan, Jing-Hon Conan, Wang, Ping-Ying
• Primary Examiner(s): MIS, DAVID C
• Application Number:
  US12/349,647
• Publication Number:
  US 20090174491A1
• Time in Patent Office: 608 Days
• Field of Search: 331/1.A, 331/8, 331 10- 12, 331 16- 18, 331/25
• US Class Current: 331/25
• CPC Class Codes: H03L 7/087 using at least two phase detectors or a frequency and phase detector in the loop
• CPC Class Codes: H03L 7/0991 the oscillator being a digital oscillator, e.g. composed of a fixed oscillator followed by a variable frequency divider H03L7/0995 takes precedence; fixed oscillators with means for selecting among various phases H03L7/0814
• CPC Class Codes: H03L 7/113 using frequency discriminator
• CPC Class Codes: H03L 7/18 using a frequency divider or counter in the loop H03L7/20, H03L7/22 take precedence

Abstract

A mixed-mode PLL is disclosed. The mixed-mode PLL comprises an analog phase correction path and a digital frequency correction path. The analog phase correction path comprises a linear phase correction unit (LPCU). The digital frequency correction path comprises a digital integral path circuit.

Claims

1. A mixed-mode PLL, comprising:

an analog phase correction path comprising a linear phase correction unit (LPCU); and

a digital frequency correction path comprising a digital integral path circuit,

wherein the digital frequency correction path tracks frequency of a reference clock in a digital domain and the linear phase correction unit generates a phase error signal to change a phase of an output of the digital frequency correction path.

2. The mixed-mode PLL as claimed in claim 1, wherein the digital frequency correction path further comprises a bang-bang phase frequency detector (PFD) coupled to the digital integral path circuit.

3. The mixed-mode PLL as claimed in claim 1, wherein the digital frequency correction path further comprises a digital controlled oscillator (DCO) coupled to the digital integral path circuit.

4. The mixed-mode PLL as claimed in claim 3, wherein the DCO is a ring oscillator or a LC oscillator.

5. The mixed-mode PLL as claimed in claim 3, wherein the DCO is controlled by the digital integral path circuit and the LPCU.

6. The mixed-mode PLL as claimed in claim 5, wherein the DCO has two inputs respectively coupled to the digital integral path circuit and the LPCU.

7. The mixed-mode PLL as claimed in claim 1, further comprising an AC coupling capacitor coupled between the LPCU and the digital frequency correction path.

8. The mixed-mode PLL as claimed in claim 1, wherein the analog phase correction path further comprises a phase frequency detector (PFD) coupled to the LPCU.

9. The mixed-mode PLL as claimed in claim 8, wherein the LPCU comprises a varactor coupled to and controlled by the PFD.

10. The mixed-mode PLL as claimed in claim 8, wherein the LPCU comprises a bias circuit, a varactor having two ends thereof coupled to the bias circuit, and a current source circuit dynamically providing a pull-up current or a pull-down current to the bias circuit.

11. The mixed-mode PLL as claimed in claim 10, wherein the bias circuit comprises a low pass filter (LPF) circuit.

12. The mixed-mode PLL as claimed in claim 8, wherein the LPCU comprises first and second bias circuits, a varactor having two ends thereof respectively coupled to the first and second bias circuits, and first and second current source circuits dynamically providing a pull-up current or a pull-down current respectively to the first and second bias circuits.

13. The mixed-mode PLL as claimed in claim 12, wherein the first and second bias circuits have same configurations and the first and second current source circuits have same configurations.

14. The mixed-mode PLL as claimed in claim 12, wherein at least one of the first and second bias circuits comprises a low pass filter (LPF) circuit.

15. A linear phase correction unit (LPCU) for a phase locked loop (PLL), comprising:

a bias circuit;

a varactor having two ends thereof coupled to the bias circuit; and

a current source circuit dynamically providing a pull-up current or a pull-down current to the bias circuit.

16. The linear phase correction unit (LPCU) as claimed in claim 15, wherein the bias circuit comprises a low pass filter (LPF) circuit.

17. A linear phase correction unit (LPCU) for a phase locked loop (PLL), comprising:

first and second bias circuits;

a varactor having two ends thereof respectively coupled to the first and second bias circuits; and

first and second current source circuits dynamically providing a pull-up current or a pull-down current respectively to the first and second bias circuits.

18. The linear phase correction unit (LPCU) as claimed in claim 17, wherein the first and second bias circuits have same configurations and the first and second current source circuits have same configurations.

19. The linear phase correction unit (LPCU) as claimed in claim 17, wherein at least one of the first and second bias circuits comprises a low pass filter (LPF) circuit.

20. A linear phase correction unit (LPCU) for a phase locked loop (PLL), comprising:

a varactor having two ends,

wherein one and the other ends of the varactor are respectively controlled by a phase up signal and a phase down signal of a phase frequency detector (PFD).