Alternative thin film transistors for liquid crystal displays

• US 7,791,679 B2
• Filed: 06/06/2003
• Issued: 09/07/2010
• Est. Priority Date: 06/06/2003
• Status: Expired due to Term

• Current Assignee: Samsung Display Company Limited (Samsung Electronics Co. Ltd.)
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Credelle, Thomas Lloyd, Elliott, Candice Hellen Brown, Schlegel, Matthew Osborne
• Primary Examiner(s): Nguyen; Dung T.
• Application Number:
  US10/456,794
• Publication Number:
  US 20040246393A1
• Time in Patent Office: 2,650 Days
• Field of Search: 349 38- 43, 349/139, 257/72, 257/59
• US Class Current: 349/42
• CPC Class Codes: G02F 1/1368 in which the switching element is a three-electrode device G02F1/136277 takes precedence
• CPC Class Codes: H01L 27/1214 comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 29/78645 with multiple gate

Abstract

Alternative thin film transistors for liquid crystal displays are disclosed. The alternative transistors can be used for panels of displays such as liquid crystal displays (LCDs), especially those having alternative pixel arrangements. These transistors can be oriented on a panel of an LCD using different, non-traditional configurations, while addressing misalignment and parasitic capacitance.

Claims

1. A device comprising a plurality of first thin film transistors and a plurality of second thin film transistors, each of said first and said second thin film transistors comprising a source electrode, a gate electrode, and a drain electrode;

wherein at least one of said first thin film transistors comprises the source electrode, the gate electrode and the drain electrode being sequentially arranged along a normal orientation away from its corresponding data line,

at least one of said second thin film transistors comprises the drain electrode, the gate electrode and the source electrode being sequentially arranged along a reverse orientation away from its corresponding data line; and

wherein, in the second thin film transistor, (i) a crossover is formed by the data line corresponding to the second thin film transistor and the gate electrode of the second thin film transistor when the data line is connected to the source electrode of the second thin film transistor;

or (ii) a first crossover is formed by the data line corresponding to the second thin film transistor and the gate line connected to the second thin film transistor when the data line is connected to the source electrode of the second thin film transistor, the first crossover being spaced apart from a second crossover where the gate line connected to the second thin film transistor crosses the data line corresponding to the second thin film transistor;

wherein said crossover in (i) or said first crossover in (ii) serve to effect substantially the same source electrode and drain electrode orientation as in said first thin film transistor;

wherein said first thin film transistors comprise a crossover to substantially balance any parasitic capacitance affected by said crossover in said second thin film transistor.

2. The device of claim 1 wherein any misalignment of thin film transistors are substantially the same for said first thin film transistors and said second thin film transistors.

3. The device of claim 1 wherein said device further comprises a plurality of pixel elements, each said pixel element connected to a thin film transistor wherein said thin film transistor comprises one of a group of thin film transistors, said group comprising said first thin film transistor and said second thin film transistor;

wherein further said pixel elements have a first corner and a second corner removed wherein further said second corner is placed where said thin film transistor connects with said pixel element.

4. The device of claim 1 wherein said data line corresponding to the first thin film transistor coincides with the data line corresponding to the second thin film transistor.

5. The device of claim 1 where the gate line connected to the second thin film transistor is also connected to the first thin film transistor.

6. A device comprising a plurality of first thin film transistors and a plurality of second thin film transistors, each of said first and said second thin film transistors comprising a source electrode, a gate electrode, and a drain electrode;

wherein at least one of said first thin film transistors comprises the source electrode, the gate electrode and the drain electrode being sequentially arranged along a normal orientation away from its corresponding data line,

at least one of said second thin film transistors comprises the drain electrode, the gate electrode and the source electrode being sequentially arranged along a reverse orientation away from its corresponding data line; and

wherein, in the second thin film transistor, (i) a crossover is formed by the data line corresponding to the second thin film transistor and the gate electrode of the second thin film transistor when the data line is connected to the source electrode of the second thin film transistor;

or (ii) a first crossover is formed by the data line corresponding to the second thin film transistor and the gate line connected to the second thin film transistor when the data line is connected to the source electrode of the second thin film transistor, the first crossover being spaced apart from a second crossover where the gate line connected to the second thin film transistor crosses the data line corresponding to the second thin film transistor;

wherein said device further comprises a plurality of pixel elements, each said pixel element connected to a thin film transistor wherein said thin film transistor comprises one of a group of thin film transistors, said group comprising said first thin film transistor and said second thin film transistor;

wherein further said pixel elements have a first corner and a second corner removed wherein further said second corner is placed where said thin film transistor connects with said pixel element;

wherein said pixel element comprises a boundary contour and said boundary contour further comprises a first portion of said boundary contour where said first corner being removed comprises a shape substantially the shape of a second portion of said boundary contour comprising said second corner comprising said thin film transistor.

7. The device of claim 6 wherein said crossover in (i) or said first crossover in (ii) serve to effect substantially the same source electrode and drain electrode orientation as in said first thin film transistor.

8. A display panel with a first side and a second side opposite to the first side, the display panel comprising:

a plurality of source lines;

a plurality of gate lines;

a plurality of pixel elements;

a plurality of thin film transistors (TFTs) each of which connects a respective pixel elements to a respective source line, each TFT comprising;

a gate electrode connected to a respective gate line;

a source electrode connected to the respective source line; and

a drain electrode connected to the respective pixel element;

wherein in top view, each gate electrode of each TFT connecting any one of said pixel elements to any one of said source lines comprises a portion positioned between the TFT'"'"'s source and drain electrodes, said portion comprising a first edge facing the drain electrode and the second edge facing the source electrode, wherein the first edge is on the first side of the second edge;

wherein at least one said gate electrode is on the first side of the respective source line, and at least one other said gate electrode is on the second side of the respective source line.

9. The display panel of claim 8 wherein at least one said TFT is on the first side of the respective source line, and at least one other said TFT is on the second side of the respective source line.

10. The display panel of claim 8 wherein in each TFT located on the second side of the respective source line, the source electrode crosses the gate electrode or the gate line.

11. The display panel of claim 9 wherein each TFT located on the first side of the respective source comprises a member extending from the respective source line and crossing the gate electrode to increase the parasitic capacitance between the respective source line and the gate electrode to improve the match between the parasitic capacitance of the TFTs located on the first side of the respective source lines and the TFTs located on the second side of the respective source lines.

12. The display panel of claim 8 wherein each pixel element comprises a first corner region on the first side of the pixel element and a second corner region on the second side of the pixel element;

wherein each TFT located on the first side of the respective source line is at least partially located in a cutout formed in the second corner region of the respective pixel element, and the respective pixel element also comprises a cutout in the second corner region, the cutout containing no part of any TFT connecting any one of said pixel elements to any one of said source lines;

wherein each TFT located on the second side of the respective source line is at least partially located in a cutout formed in the first corner region of the respective pixel element, and the respective pixel element also comprises a cutout in the first corner region, the cutout containing no part of any TFT connecting any one of said pixel elements to any one of said source lines.

13. A display panel with a first side and a second side opposite to the first side, the display panel comprising:

a plurality of source lines;

a plurality of gate lines;

a plurality of pixel elements;

a plurality of thin film transistors (TFTs) each of which connects a respective pixel elements to a respective source line, each TFT comprising;

a gate electrode connected to a respective gate line;

a source electrode connected to the respective source line; and

a drain electrode connected to the respective pixel element;

wherein in top view, each drain electrode of each TFT connecting any one of said pixel elements to any one of said source lines is connected to the respective pixel element on the first side of the gate electrode;

wherein at least one said gate electrode is on the first side of the respective source line, and at least one other said gate electrode is on the second side of the respective source line.

14. The display panel of claim 13 wherein each drain electrode of each TFT connecting any one of said pixel elements to any one of said source lines is located on the first side of the gate electrode.

15. The display panel of claim 13 wherein at least one said TFT is on the first side of the respective source line, and at least one other said TFT is on the second side of the respective source line.

16. The display panel of claim 13 wherein in each TFT located on the second side of the respective source line, the source electrode crosses the gate electrode or the gate line.

17. The display panel of claim 16 wherein each TFT located on the first side of the respective source comprises a member extending from the respective source line and crossing the gate electrode to increase the parasitic capacitance between the respective source line and the gate electrode to improve the match between the parasitic capacitance of the TFTs located on the first side of the respective source lines and the TFTs located on the second side of the respective source lines.

18. The display panel of claim 13 wherein each pixel element comprises a first corner region on the first side of the pixel element and a second corner region on the second side of the pixel element;

wherein each TFT located on the first side of the respective source line is at least partially located in a cutout formed in the second corner region of the respective pixel element, and the respective pixel element also comprises a cutout in the second corner region, the cutout containing no part of any TFT connecting any one of said pixel elements to any one of said source lines;

wherein each TFT located on the second side of the respective source line is at least partially located in a cutout formed in the first corner region of the respective pixel element, and the respective pixel element also comprises a cutout in the first corner region, the cutout containing no part of any TFT connecting any one of said pixel elements to any one of said source lines.