Biased sensing module

• US 7,791,970 B2
• Filed: 09/18/2007
• Issued: 09/07/2010
• Est. Priority Date: 09/18/2006
• Status: Active Grant

• Current Assignee: STMicroelectronics Pvt Ltd. (STMicroelectronics NV)
• Original Assignee: STMicroelectronics Pvt Ltd. (STMicroelectronics NV)
• Inventors: Ahmad, Nasim, Roy, Tanmoy
• Primary Examiner(s): Nguyen; Tuan T.
• Application Number:
  US11/856,801
• Publication Number:
  US 20080212354A1
• Time in Patent Office: 1,085 Days
• Field of Search: 365/203, 365/205, 365/189.02
• US Class Current: 365/203
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 7/065 Differential amplifiers of latching type
• CPC Class Codes: G11C 7/12 Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines

Abstract

A circuit includes a first pre-charge module, a first multiplexer module, a second pre-charge module, a second multiplexer module, a sense amplifier circuit, a third pre-charge module, an output module. The circuit is operatively coupled to a first core block and a second core block to provide the desired matching characteristics. The first core block and the second core block are memory blocks used for storing data bits for read-write operations. The circuit utilizes a unique operational coupling with one of the core blocks to provide the matching characteristics.

Claims

1. A sensing circuit comprising:

a first pre-charge module and a first core block coupled thereto;

a first pass transistor;

a first multiplexer module coupled between said first pre-charge module and said first pass transistor;

a second pre-charge module and a second core block coupled thereto;

a second pass transistor;

a second multiplexer module coupled between said second pre-charge module and said second pass transistor;

a sense amplifier circuit coupled between said first multiplexer module and said second multiplexer module and having first and second inputs to receive inputs through said first pass transistor and said second pass transistor, respectively; and

a third pre-charge module coupled to said first and second inputs of said sense amplifier circuit.

2. The sensing circuit of claim 1, further comprising an output module coupled to said sense amplifier and to provide an output signal.

3. The sensing circuit of claim 1, wherein said first pre-charge module comprises at least one NMOS transistor.

4. The sensing circuit of claim 1, wherein said second pre-charge module comprises at least one NMOS transistor.

5. The sensing circuit of claim 1, wherein said first pass transistor comprises a PMOS transistor.

6. The sensing circuit of claim 1, wherein said second pass transistor comprises a PMOS transistor.

7. The sensing circuit of claim 1, wherein said third pre-charge module comprises:

a third pass transistor having a source terminal coupled to a voltage source, a drain terminal coupled to said first input of said sense amplifier, and a gate terminal coupled to a node;

a fourth pass transistor having a source terminal coupled to said voltage source, a drain terminal coupled to the second input of the sense amplifier, and a gate terminal coupled to the gate terminal of the third pass transistor through the node; and

a fifth pass transistor having a source terminal coupled to the drain terminal of the fourth pass transistor, a drain terminal coupled to the drain terminal of the third transistor, and a gate terminal coupled to the gate of the third pass transistor and the fourth pass transistor through said node.

8. The sensing circuit of claim 7, wherein said third pass transistor comprises a PMOS transistor.

9. The sensing circuit of claim 7, wherein said fourth pass transistor comprises a PMOS transistor.

10. The circuit of claim 7, wherein said fifth pass transistor comprises a PMOS transistor.

11. A read only memory (ROM) comprising:

a plurality of memory blocks for storing data bits; and

a biased sensing circuit coupled to said plurality of memory blocks comprising;

a first pre-charge module and a first core block coupled thereto,

a first pass transistor,

a first multiplexer module coupled between said first pre-charge module and said first pass transistor,

a second pre-charge module and a second core block coupled thereto,

a second pass transistor,

a second multiplexer module coupled between the second pre-charge module and said second pass transistor,

a sense amplifier circuit coupled between said first multiplexer module and said second multiplexer module and having first and second inputs to receive inputs through said first pass transistor and said second pass transistor, respectively, and

a third pre-charge module coupled to said first and second inputs of said sense amplifier circuit.

12. The ROM of claim 11, wherein said biased sensing circuit further comprises an output module coupled to said sense amplifier to provide an output signal.

13. The ROM of claim 11, wherein said first pre-charge module comprises at least one NMOS transistor;

and wherein said second pre-charge module comprises at least one NMOS transistor.

14. The ROM of claim 11, wherein said first pass transistor comprises a NMOS transistor;

and wherein said second pass transistor comprises a NMOS transistor.

15. The ROM of claim 11, wherein said third pre-charge module comprises:

a third pass transistor having a source terminal coupled to a voltage source, a drain terminal coupled to said first input of said sense amplifier, and a gate terminal coupled to a node;

a fourth pass transistor having a source terminal coupled to said voltage source, a drain terminal coupled to the second input of the sense amplifier, and a gate terminal coupled to the gate terminal of the third pass transistor through the node; and

a fifth pass transistor having a source terminal coupled to the drain terminal of the fourth pass transistor, a drain terminal coupled to the drain terminal of the third transistor, and a gate terminal coupled to the gate of the third pass transistor and the fourth pass transistor through said node.

16. A method of making a circuit for sensing signals comprising:

coupling a first pre-charge module between a first core block and a first multiplexer;

coupling a second pre-charge module between a second core block and a second multiplexer;

coupling a first pass transistor coupled between the first multiplexer and a first input of a sense amplifier;

coupling a second pass transistor between the second multiplexer and a second input of the sense amplifier;

coupling a third pre-charge module to the first and second inputs of the sense amplifier; and

coupling an output module to the sense amplifier;

the sense amplifier to receive signals through the first and second pass transistors.

17. The method of claim 16, wherein the first pre-charge module comprises at least one NMOS transistor.

18. The method of claim 16, wherein the first pass transistor comprises a PMOS transistor.

19. The method of claim 16, wherein the third pre-charge module comprises:

a third pass transistor having a source terminal coupled to a voltage source, a drain terminal coupled to the first input of the sense amplifier, and a gate terminal coupled to a node;

a fourth pass transistor having a source terminal coupled to the voltage source, a drain terminal coupled to the second input of the sense amplifier, and a gate terminal coupled to the gate terminal of the third pass transistor through the node; and

a fifth pass transistor having a source terminal coupled to the drain terminal of the fourth pass transistor, a drain terminal coupled to the drain terminal of the third transistor, and a gate terminal coupled to the gate of the third pass transistor and the fourth pass transistor through the node.