Method and system for routing and filtering network data packets in fibre channel systems

• US 7,792,115 B2
• Filed: 07/20/2004
• Issued: 09/07/2010
• Est. Priority Date: 07/21/2003
• Status: Expired due to Fees

• Current Assignee: Marvell Asia Pte Limited (Marvell Technology Group Limited)
• Original Assignee: QLogic Corporation (Marvell Technology Group Limited)
• Inventors: Dropps, Frank R., Ross, Edward C., Betker, Steven M.
• Primary Examiner(s): Kumar; Pankaj
• Assistant Examiner(s): SMITH, MARCUS
• Application Number:
  US10/894,546
• Publication Number:
  US 20050044267A1
• Time in Patent Office: 2,240 Days
• Field of Search: None
• US Class Current: 370/392
• CPC Class Codes: H04L 69/324 in the data link layer [OSI layer 2], e.g. HDLC

Abstract

A fiber channel switch element with an alias cache is provided for routing and filtering frames. The alias cache includes plural entries including a control word having plural fields including an action code for routing frames; an alias word that is compared to incoming frame data using a frame byte compare block; and a bit mask generator for filtering bit combinations from the frame byte compare block; and a depth match block for determining equality between a control word depth field and incoming frame depth field. Frame data comparison is performed on a bit by bit or byte-by-byte basis. An alias cache entry also includes prerequisite data to determine if results of a different entry are to be used to determine an entry match. The action code routes a frame to a processor, discards a frame, sets a status for inspecting a frame or routes a frame based on a standard Fiber Channel addressing scheme.

Claims

1. A method for processing frames, comprising:

(a) receiving a frame at a port of a switch element;

(b) simultaneously comparing incoming frame information with a plurality of fields of an alias cache entry from among a plurality of alias cache entries that are configured by a switch element processor;

wherein the alias cache entry includes a control word based on which the frame is processed by the switch element; and

wherein the control word includes a word depth field for identifying which word in the frame is compared to the alias cache entry field, and a programmed action code that determines an action based on the comparison to route the frame to a destination based on a matching alias cache entry, discard the frame, set a status for inspecting the frame and route the frame based on a standard addressing scheme;

(c) performing a word depth match by comparing incoming frame word depth with a programmed word depth of the alias cache entry; and

(d) routing the frame based on the action code of the alias cache entry.

2. The method of claim 1, wherein the frame data comparison is performed on a bit by bit or byte-by-byte basis, based on the settings in the alias cache entry.

3. The method of claim 1, wherein a plurality of frame words are compared before any action is taken.

4. The method of claim 1, wherein the alias cache entry includes prerequisite data to determine if a result from a comparison with a different alias cache entry at a different fame word depth is used to determine if the frame information has an entry match.

5. A system, comprising:

a switch element receiving a frame from another device, the switch element comprising;

an alias cache having a plurality of entries for simultaneously comparing frame information with a plurality of fields of an alias cache entry that are configured by a switch element processor;

wherein the alias cache entry includes a control word having a plurality of fields based on which the frame is processed by the switch element; and

wherein the control word includes a word depth field identifying which word in the frame is compared to the alias cache entry, and a programmed action code that determines an action based on the comparison to route the frame to a destination based on a matching alias cache entry, discard the frame, set a status for inspecting the frame and route the frame based on a standard addressing scheme;

a frame byte compare block for comparing frame information with an alias cache entry word;

a bit mask generator for filtering bit combinations received from the frame byte compare block; and

a depth match block for determining equality between a control word depth field and an incoming frame depth field.

6. The system of claim 5, further comprising:

a valid and status generator module that receives plural inputs from the alias cache entry and the depth match block and generates an output signal that is sent to an encoder module.

7. The system of claim 5, wherein comparison of information in the frame is performed on a bit by bit or byte-by-byte basis, based on the settings in the alias cache entry.

8. The system of claim 5, wherein a plurality of frame words are compared before any action is taken.

9. The system of claim 5, wherein the alias cache entry includes prerequisite data to determine if a result from a comparison with a different alias cache entry at a different fame word depth is used to determine if the frame information has an entry match.

10. A switch element, comprising:

an alias cache having a plurality of entries for simultaneously comparing frame information with a plurality of fields of an alias cache entry that are configured by a switch element processor;

wherein the alias cache entry includes a control word having a plurality of fields based on which the frame is processed by the switch element; and

wherein the control word includes a word depth field identifying which word in the frame is compared to the alias cache entry, and a programmed action code that determines an action based on the comparison to route the frame to a destination based on a matching alias cache entry, discard the frame, set a status for inspecting the frame and route the frame based on a standard addressing scheme;

a frame byte compare block for comparing frame information with an alias cache entry word;

a bit mask generator for filtering bit combinations received from the frame byte compare block; and

a depth match block for determining equality between a control word depth field and an incoming frame depth field.

11. The switch element of claim 10, further comprising:

a valid and status generator module that receives plural inputs from the alias cache entry and the depth match block and generates an output signal that is sent to an encoder module.

12. The switch element of claim 10, wherein comparison of information in the frame is performed on a bit by bit or byte-by-byte basis.

13. The switch element of claim 10, wherein a plurality of frame words are compared before any action is taken.

14. The switch element of claim 10, wherein the alias cache entry includes prerequisite data to determine if a result from a comparison with a different alias cache entry at a different fame word depth is used to determine if the frame information has an entry match.

15. A method for processing frames, comprising:

(a) receiving a frame at a port of a switch element;

(b) determining if the frame is pre-destined for a switch processor;

(c) if the incoming frame is not pre-destined for the switch processor, simultaneously comparing frame information with a plurality of fields of an alias cache entry from among a plurality of alias cache entries that are configured by a switch element processor;

wherein the alias cache entry includes a control word based on which the frame is processed by the switch element; and

wherein the control word includes a word depth field for identifying which word in the frame is compared to the alias cache entry field, and a programmed action code that determines an action based on the comparison to route the frame to a destination based on a matching alias cache entry, discard the frame, set a status for inspecting the frame and route the frame based on a standard addressing scheme;

(d) performing a word depth match by comparing the frame'"'"'s word depth with a programmed word depth in the alias cache entry; and

(d) routing the frames based on the action code of the alias cache entry.

16. The method of claim 15, wherein the frame data comparison is performed on a bit by bit or byte-by-byte basis, based on the settings in the alias cache entry.

17. The method of claim 15, wherein a plurality of frame words are compared before any action is taken.

18. The method of claim 15, wherein the alias cache entry includes prerequisite data to determine if a result from a comparison with a different alias cache entry at a different fame word depth is used to determine if the frame information has an entry match.