Hardware-centric medium access control (MAC) device

• US 7,792,141 B2
• Filed: 01/08/2007
• Issued: 09/07/2010
• Est. Priority Date: 01/08/2007
• Status: Active Grant

• Current Assignee: Nordic Semiconductor ASA
• Original Assignee: Hellosoft Incorporated (Imagination Technologies Group Ltd.)
• Inventors: Barman, Kaushik, Aldaz, Luis, Aldaz, legal representative Sr., Johnson, Allan A., Malladi, Raghavendra
• Primary Examiner(s): Chang; Kent
• Assistant Examiner(s): Siddiqui; Kashif
• Application Number:
  US11/651,330
• Publication Number:
  US 20080165798A1
• Time in Patent Office: 1,338 Days
• Field of Search: 370/231, 370/328, 370/338, 370351-352, 370/389, 370/392, 370401-405, 370/463, 455/90.2
• US Class Current: 370/463
• CPC Class Codes: H04L 65/1053 IP private branch exchange [PBX] functionality entities or arrangements circuit switched PBXs H04M3/00
• CPC Class Codes: H04L 65/70 Media network packetisation
• CPC Class Codes: H04L 69/16 Implementation or adaptation of Internet protocol [IP], of transmission control protocol [TCP] or of user datagram protocol [UDP]
• CPC Class Codes: H04M 1/2535 adapted for voice communication over an Internet Protocol [IP] network Voice over Internet Protocol (VoIP) network equipment and services H04M7/006; implementation or adaptation of Internet protocol [IP], of transmission control protocol [TCP] or of user datagram protocol [UDP] H04L69/16

Abstract

A hardware-centric medium access control (MAC) device comprises a control plane module and a hardware media access planed module. The control plane module is for providing control functions of the hardware-centric MAC device. The hardware media access plane module communicatively coupled to the control plane module is for performing real-time data communication functions without requiring a microprocessor.

Claims

1. A voice communication device comprising:

a microprocessor;

a memory communicatively coupled to said microprocessor;

a wireless communication module communicatively coupled to said microprocessor, said wireless communication module for receiving and transmitting voice traffic over a wireless connection and comprising;

a physical layer (PHY) device; and

a hardware-centric medium access control (MAC) device implemented as a portion of a system on a chip (SOC) communicatively coupled to said PHY device and conditionally activated from a shutdown state by said PHY device, wherein said MAC device is configured to perform real-time voice communication functions using the SOC, said hardware-centric MAC comprising;

a control plane module for providing control functions of said hardware-centric MAC device; and

a hardware media access plane module communicatively coupled to said control plane module and for performing real-time data and voice communication functions without requiring a microprocessor, said hardware media access plane module comprising;

a beacon process module to receive and to filter out unwanted voice traffic packets in hardware without use of other portions of said hardware-centric MAC or using said microprocessor, such that said microprocessor remains in a sleep mode during beacon processing by said beacon process module;

a de-fragmentation engine communicatively coupled with said beacon process module and for providing real-time de-fragmentation, in gate logic, of received voice traffic packets that are not filtered out by said beacon process module;

an encryption/decryption engine coupled with said de-fragmentation engine to provide on-the-fly encryption/decryption of voice traffic packets with real-time logic based key retrieval merged with on-the-fly fragmentation and defragmentation; and

a fragmentation engine communicatively coupled with said encryption/decryption engine and for providing real-time fragmentation, in gate logic, of transmit voice traffic packets.

2. The voice communication device of claim 1 wherein said hardware media access plane module is implemented in gate logic, such that real-timing requirements of said hardware-centric MAC device are handled in gate logic.

3. The voice communication device of claim 2 wherein said control plane module is implemented in gate logic.

4. The voice communication device of claim 2 wherein at least a portion of said control plane module is implemented in programmable hardware.

5. The voice communication device of claim 1 wherein said microprocessor is operable to provide control functionality of said MAC device.

6. The voice communication device of claim 5 wherein said microprocessor is operable to execute a MAC driver for controlling configuration settings of said hardware-centric MAC device.

7. The voice communication device of claim 6 wherein said microprocessor is not operable to execute said MAC driver during real-time data communication.

8. The voice communication device of claim 1 wherein said control plane module comprises a real-time logic (RTL) station management entity (SME) for monitoring features of said hardware-centric MAC device.

9. The voice communication device of claim 1, wherein said sleep mode comprises a shut down of a core of said microprocessor.

10. A wireless transceiver comprising:

a physical layer (PHY) device implemented as a portion of a system on a chip (SOC); and

a hardware-centric medium access control (MAC) device implemented as a portion of said system in a chip (SOC) and communicatively coupled with said PHY device, said hardware-centric MAC device conditionally activated from a shutdown state by said PHY device, said hardware-centric MAC device comprising;

a control plane module for providing control functions of said hardware-centric MAC device; and

a hardware media access plane module communicatively coupled to said control plane module and for performing real-time data communication functions using the SOC, said hardware media access plane module comprising;

a beacon process module to receive and to filter out unwanted data packets in hardware without use of other portions of said hardware-centric MAC or using said microprocessor;

a de-fragmentation engine communicatively coupled with said beacon process module and for providing real-time de-fragmentation, in gate logic, of received data packets that are not filtered out by said beacon process module;

an encryption/decryption engine coupled with said de-fragmentation engine to provide on-the-fly encryption/decryption of data packets with real-time logic based key retrieval merged with on-the-fly fragmentation and defragmentation; and

a fragmentation engine communicatively coupled with said encryption/decryption engine and for providing real-time fragmentation, in gate logic, of transmit data packets.