Methods and apparatus for calibrating output voltage levels associated with current-integrating summing amplifier

• US 7,792,185 B2
• Filed: 02/07/2007
• Issued: 09/07/2010
• Est. Priority Date: 02/07/2007
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Park, Matthew J., Bulzacchelli, John Francis
• Primary Examiner(s): Lugo; David B
• Application Number:
  US11/672,309
• Publication Number:
  US 20080187037A1
• Time in Patent Office: 1,308 Days
• Field of Search: 375/292, 375/232, 375/233
• US Class Current: 375/233
• CPC Class Codes: G06G 7/18 for integration or differentiation; for forming integrals G06G7/19 takes precedence
• CPC Class Codes: H03K 5/02 by amplifying H03K5/04 takes precedence

Abstract

Methods and apparatus are disclosed for calibrating summing amplifiers based on current integration. For example, apparatus for calibrating output voltage levels of a current-integrating summing amplifier includes the following components. A duplicate integrator circuit is provided, wherein the duplicate integrator circuit replicates an integrator circuit of the current-integrating summing amplifier. A comparing circuit, coupled to the duplicate integrator circuit, is provided for comparing at least one output voltage level generated by the duplicate integrator circuit with a reference voltage level. A feedback loop circuit, coupled to the comparing circuit and the duplicate integrator circuit, is provided for adjusting at least one bias signal of the duplicate integrator circuit so that the output voltage level generated by the duplicate integrator circuit matches the reference voltage level, wherein the bias signal is applied to the integrator circuit of the current-integrating summing amplifier thereby calibrating output signal components due to multiple input signals of the current-integrating summing amplifier.

Claims

1. Apparatus for calibrating output voltage levels of a current-integrating summing amplifier, comprising:

a duplicate integrator circuit, wherein the duplicate integrator circuit replicates an integrator circuit of the current-integrating summing amplifier;

a comparing circuit coupled to the duplicate integrator circuit, the comparing circuit comparing at least one output voltage level generated by the duplicate integrator circuit with a reference voltage level; and

a feedback loop circuit coupled to the comparing circuit and the duplicate integrator circuit, the feedback loop circuit adjusting at least one bias signal of the duplicate integrator circuit so that the output voltage level generated by the duplicate integrator circuit matches the reference voltage level, wherein the bias signal is applied to the integrator circuit of the current-integrating summing amplifier thereby calibrating output signal components due to multiple input signals of the current-integrating summing amplifier.

2. The apparatus of claim 1, wherein the bias signal of the feedback loop circuit is used to derive multiple current signals of the current-integrating summing amplifier.

3. The apparatus of claim 2, wherein the multiple current signals are derived in accordance with a scale factor representative of a ratio of a capacitance value and an integration period associated with the current-integrating summing amplifier such that the output signal components are stabilized with respect to at least one of the capacitance value and the integration period.

4. The apparatus of claim 2, wherein the multiple current signals are derived via a current mirror circuit.

5. The apparatus of claim 1, wherein the feedback loop circuit comprises a digital feedback loop circuit.

6. The apparatus of claim 5, wherein the comparing circuit comprises at least one clocked comparator.

7. The apparatus of claim 6, wherein the digital feedback loop circuit further comprises:

a finite state machine, coupled to the clocked comparator, for generating a digital bias current signal based on a result from the clocked comparator; and

at least one current digital-to-analog converter coupled to the finite state machine for converting the digital bias current signal to at least one analog bias signal.

8. The apparatus of claim 7, wherein the digital feedback loop circuit further comprises at least a second current digital-to-analog converter coupled to the finite state machine for converting the digital bias current signal to at least a second analog bias signal.

9. The apparatus of claim 1, wherein the feedback loop circuit and the duplicate integrator circuit are configured such that the bias signal is adjusted so that the lowest possible output voltage level generated by the integrator circuit of the current-integrating summing amplifier is regulated to the reference voltage level.

10. The apparatus of claim 1, wherein the feedback loop circuit comprises an analog feedback loop circuit.

11. The apparatus of claim 10, wherein the comparing circuit comprises at least one sample and hold circuit.

12. The apparatus of claim 10, wherein the analog feedback loop circuit comprises an operational amplifier for generating an analog bias signal based on the output voltage level generated by the duplicate integrator circuit.

13. A decision feedback equalizer, comprising:

a current-integrating summing amplifier for summing input signals and tap weight-adjusted feedback signals;

a calibration circuit coupled to the current-integrating summing amplifier and configured to calibrate output signal components due to multiple input signals of the current-integrating summing amplifier; and

a decision block coupled to the current-integrating summing amplifier for detecting bits in the input signals;

wherein the calibration circuit further comprises;

a duplicate integrator circuit, wherein the duplicate integrator circuit replicates an integrator circuit of the current-integrating summing amplifier;

a comparing circuit coupled to the duplicate integrator circuit, the comparing circuit comparing at least one output voltage level generated by the duplicate integrator circuit with a reference voltage level; and

a feedback loop circuit coupled to the comparing circuit and the duplicate integrator circuit, the feedback loop circuit adjusting at least one bias signal of the duplicate integrator circuit so that the output voltage level generated by the duplicate integrator circuit matches the reference voltage level, wherein the bias signal is applied to the integrator circuit of the current-integrating summing amplifier thereby calibrating output signal components due to multiple input signals of the current-integrating summing amplifier.

14. The decision feedback equalizer of claim 13, wherein the bias signal of the feedback loop circuit is used to derive multiple current signals of the current-integrating summing amplifier.

15. The decision feedback equalizer of claim 14, wherein the multiple current signals are derived in accordance with a scale factor representative of a ratio of a capacitance value and an integration period associated with the current-integrating summing amplifier such that the output signal components are stabilized with respect to at least one of the capacitance value and the integration period.

16. The decision feedback equalizer of claim 14, wherein the multiple current signals are derived via a current mirror circuit.

17. The decision feedback equalizer of claim 13, wherein the feedback loop circuit comprises a digital feedback loop circuit.

18. The decision feedback equalizer of claim 13, wherein the feedback loop circuit comprises an analog feedback loop circuit.