Edge-aligned ratio counter

• US 7,792,650 B2
• Filed: 12/16/2004
• Issued: 09/07/2010
• Est. Priority Date: 09/02/2003
• Status: Expired due to Fees

• Current Assignee: CSR Technology Incorporated (Qualcomm, Inc.)
• Original Assignee: SIRF Technology Incorporated (Qualcomm, Inc.)
• Inventors: Gronemeyer, Steven A., Underbrink, Paul
• Primary Examiner(s): Wachsman; Hal D
• Application Number:
  US11/014,684
• Publication Number:
  US 20060047459A1
• Time in Patent Office: 2,091 Days
• Field of Search: 702 75- 79, 702/71, 702/64, 702/66, 702/70, 702/73, 702/74, 702/125, 702/124, 702/178, 702/189, 702/78, 701/213, 701/214
• US Class Current: 702/79
• CPC Class Codes: G01S 19/23 Testing, monitoring, correcting or calibrating of receiver elements

Abstract

An Edge-Aligned Ratio Counter (EARC) that includes at least one processor coupled to at least one counter circuit is provided for determining a ratio between two clock signals by receiving a first and a second value in response to a first clock signal and generating a control signal under control of the loaded value by counting the pulses of the first clock signal and a second clock signal and captures the count of each clock signal in response to the control signal and determining a ratio between a frequency of the first clock signal and a frequency of the second clock signal using the differences of the captured counts taken at two different occurrences of the control signal.

Claims

1. A circuit comprising

at least one processor coupled to at least one counter circuit,

the at least one counter circuit receiving one of a first value and a second value in response to a first clock signal and generating a control signal under control of the received value,

the at least one counter circuit counting pulses of the first clock signal and a second clock signal and capturing the count of each of the first and the second clock signals in response to the control signal and determining a ratio between a frequency of the first clock signal and a frequency of the second clock signal using the captured count.

2. The circuit of claim 1, further comprising a first receiver having a first clock for generating the first clock signal.

3. The circuit of claim 2, wherein the first receiver is a telecommunications receiver.

4. The circuit of claim 2, further comprising a second receiver having a second clock for generating the second clock signal.

5. The circuit of claim 4, wherein the second receiver is a Global Positioning System (GPS) receiver.

6. The circuit of claim 1, further comprising at least one register for storing the first and second values.

7. The circuit of claim 1, wherein the at least one counter circuit comprises a first register for storing the first value and a second register for storing the second value.

8. The circuit of claim 7, further comprising a control signal generator that includes a first input for receiving input of the first value stored in the first register, a second input for receiving the second value stored in the second register, a third input for receiving the first clock signal, a fourth input for receiving the second clock signal and an output for outputting the control signal in accordance with the first and second values stored in the first and second register and the first and the second clock signals.

9. The circuit of claim 8, wherein the control signal generator further comprises:

at least one switch responsive to an edge transition signal, for selecting between the first input from the first register and the second input from the second register;

at least one decrementing counter for alternately receiving the value from the first or second register and decrementing the received value in synchronization with the first clock signal and generating an enable signal when the received value reaches zero;

at least one flip-flop responsive to the enable signal for generating the edge transition signal in accordance with the first clock signal and the second clock signal; and

at least one pulse generator responsive to the edge transition signal, for outputting the control signal to the count capture unit.

10. The circuit of claim 8, wherein the control signal generator generates the control signal when a transitional edge of the first clock signal is approximately coincidental with a transitional edge of the second clock signal.

11. The circuit of claim 10, further comprising a count capture unit responsive to the control signal output from the control signal generator for capturing values representative of the number of clock cycles of the first and the second clock signal, that occur within a given time period.

12. The circuit of claim 11, wherein the count capture unit further comprises:

a first incrementing counter for counting the pulses of the first clock signal;

a second incrementing counter for counting the pulses of the second clock signal;

a first latch for storing the count value for the first incrementing counter in response to the control signal; and

a second latch for storing the count value of the second incrementing counter in response to the control signal.

13. The circuit of claim 1, wherein the first value represents an approximation of time expressed as number of cycles of the first clock signal and the second value represents an approximation of the time expressed as number of cycles of the second clock signal.

14. The circuit of claim 13, wherein the first and the second values are selected in accordance with calculations based upon the principles of convergents of continued fractions.

15. The circuit of claim 13, wherein the first and the second values are selected with predetermined values associated with the number of cycles of the first clock signal and the number of cycles of the second clock signal and result in relatively coarse measurement.

16. The circuit of claim 1, wherein the first and the second clock signals are asynchronous.

17. A device comprising:

at least one processor;

at least one memory area coupled to the at least one processor and storing values representative of a first clock signal and a second clock signal; and

at least one counter circuit coupled to the at least one processor and selectively receiving the stored values and generating a control signal under control of the stored values, the at least one counter circuit counting pulses of the first and the second clock signals, capturing the count of each of the first and the second clock signals in response to the control signal and determining a ratio between a frequency of the first and the second clock signals using the captured count.

18. The device of claim 17, further comprising a control signal generator that includes a first input for receiving a first stored value of a first register, a second input for receiving a second stored value of a second register, a third input for receiving the first clock signal, a fourth input for receiving the second clock signal, and an output for outputting the control signal in accordance with the first and the second values stored in the first and the second registers, respectively, and the first and the second clock signals.

19. The device of claim 18, wherein the first stored value represents an approximation of the frequency of the first clock signal and the second stored value represents an approximation of the frequency of the second clock signal, wherein the first and second stored values are selected in accordance with calculations based upon the principles of convergents of continued fractions.

20. The device of claim 18, wherein the control signal generator generates the control signal when a transitional edge of the first clock signal is approximately coincidental with a transitional edge of the second clock signal.

21. The device of claim 17, further comprising a count capture circuit responsive to the control signal for capturing values representative of the number of clock cycles of the first and the second clock signal that occur within a given time period.

22. A device comprising:

means for receiving one of a first and second value in response to a first clock signal;

means for generating a control signal under control of the received value;

means for counting pulses of a first clock signal and a second clock signal and capturing the count of each of the first and second clock signals in response to the control signal;

means for determining a ratio between a frequency of the first clock signal and a frequency of the second clock signal using the captured count; and

means for generating the control signal when a transitional edge of the first clock signal is approximately coincidental with a transitional edge of the second clock signal.

23. The device of claim 22, further comprising:

means for capturing values representative of the number of clock cycles of the first and the second clock signal that occur within a given time period in response to the control signal.

24. The device of claim 22, further comprising means for storing at least one of the first and second values in at least one register.

25. A method comprising:

receiving one of a first and a second value in response to a first clock signal;

generating a control signal under control of the received value;

counting pulses of the first clock signal and a second clock signal and capturing the count of each clock of the first and the second dock signals in response to the control signal; and

determining a ratio between a frequency of the first clock signal and a frequency of the second clock signal using differences of successive captured counts, respectively.

26. The method of claim 25, further comprising:

generating the control signal when a transitional edge of the first clock signal is approximately coincidental with a transitional edge of the second clock signal.

27. The method of claim 25, further comprising:

capturing values representative of the number of clock cycles of the first and the second clock signal that occur within a given time period in response to the control signal.

28. The method of claim 25, further comprising storing at least one of the first and second values in at least one register.

29. The method of claim 25, wherein the first value represents an approximation of time in terms of cycles of the first clock signal and the second value represents an approximation of time in terms of cycles of the second clock signal, wherein the first and second values are selected in accordance with calculations based upon the principles of convergents of continued fractions.

30. The method of claim 29 wherein:

a frequency ratio is a ratio of the frequency of the first clock signal and an estimate of the frequency of the second clock signal, the frequency ratio being a sequence of continued fraction expansion where;

frequency ratio=a₀+[1/(a₁+[1/(a₂+ . . . +1/a_n)]), where n=number of terms in the sequence of continued fraction expansion;

the method further comprising;

generating a sequence of rational fractions having a numerator and a denominator, each rational fraction being defined as the frequency ratio solved for each integer between 0 and n;

calculating an error for each rational fraction; and

selecting a pair of consecutive denominators in the sequence of rational fractions corresponding to a lowest non-zero error as the first and second values.

31. The method of claim 29 wherein:

one of the first and the second values generates a coarse slew and the other of the first and the second values generates a fine slew;

the first clock signal generates a reference frequency and the second clock signal generates a sampled frequency and the sampled frequency is different from a nominal frequency value for the sampled frequency such that the coarse slew is greater than half of a period of an estimated slowest value of the sampled frequency;

a frequency ratio is a ratio of the frequency of the first clock signal and an estimate of the frequency of the second clock signal, the frequency ratio being a sequence of continued fraction expansion where;

frequency ratio=a₀+[1/(a₁+[1/(a₂+ . . . +1/a_n)]), where n=number of terms in the sequence of continued fraction expansion;

the method further comprising;

generating a sequence of rational fractions having a numerator and a denominator, each rational fraction being defined as the frequency ratio solved for each integer between 0 and n;

calculating an error for each rational fraction; and

selecting a pair of consecutive denominators in the sequence of rational fractions corresponding to a greater error than a lowest non-zero error as the first and the second values, such that the coarse slew is then shorter than a half period of the slowest expected sampled clock value.