System and method for programmable bank selection for banked memory subsystems

• US 7,793,038 B2
• Filed: 06/26/2007
• Issued: 09/07/2010
• Est. Priority Date: 06/26/2007
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Hoenicke, Dirk, Sugavanam, Krishnan, Gara, Alan G., Ohmacht, Martin, Chen, Dong, Giampapa, Mark E., Blumrich, Matthias A., Salapura, Valentina
• Primary Examiner(s): Chery; Mardochee
• Application Number:
  US11/768,805
• Publication Number:
  US 20090006718A1
• Time in Patent Office: 1,169 Days
• Field of Search: 711/104, 711/105
• US Class Current: 711/105
• CPC Class Codes: G06F 12/0804 with main memory updating G06F12/0806 takes precedence
• CPC Class Codes: G06F 12/0851 Cache with interleaved addressing
• CPC Class Codes: G06F 12/0897 with two or more cache hierarchy levels with multilevel cache hierarchies G06F12/0811
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A programmable memory system and method for enabling one or more processor devices access to shared memory in a computing environment, the shared memory including one or more memory storage structures having addressable locations for storing data. The system comprises: one or more first logic devices associated with a respective one or more processor devices, each first logic device for receiving physical memory address signals and programmable for generating a respective memory storage structure select signal upon receipt of pre-determined address bit values at selected physical memory address bit locations; and, a second logic device responsive to each of the respective select signal for generating an address signal used for selecting a memory storage structure for processor access. The system thus enables each processor device of a computing environment memory storage access distributed across the one or more memory storage structures.

Claims

1. A programmable memory system for enabling one or more processor devices access to shared memory in a computing system, said shared memory comprising one or more memory storage structures having addressable locations for storing data for said one or more processor devices, said system comprising:

one or more first logic devices associated with a respective said one or more processor devices, each one or more first programmable logic devices for receiving physical memory address bits, each one or more first logic devices programmed to generate a respective memory structure select signal upon receipt of address bit values at pre-determined physical memory address bit locations;

a second logic device responsive to each said respective select signal for generating an address signal used for selecting a memory storage structure for processor access, wherein each processor device of said computing system enables memory storage access distributed across said one or more memory storage structures, and,

means for receiving unselected bit values of said received physical memory address for generating an offset bit vector signal used to enable processor device access to memory locations within a selected memory storage structure,

wherein each said respective select signal comprises an asserted bit value output,

said second logic device for concatenating one or more said asserted bit value outputs from said associated first logic devices to generate a bit vector for use as said address signal used to select a memory storage structure.

2. The programmable memory system as claimed in claim 1, wherein said address bit values at pre-determined physical memory address bit locations are programmable for enabling a single processor exclusive access to a single memory storage structure.

3. The programmable memory system as claimed in claim 1, wherein each said one or more associated first logic device includes a multiplexer device programmed to respond to said address bit values at pre-determined physical memory address bit locations.

4. The programmable memory system as claimed in claim 1, wherein each said one or more associated first logic device implements logic for applying a hash function to said physical memory address bits.

5. The programmable memory system as claimed in claim 4, wherein each said one or more associated first e logic device comprises an XOR reduction tree for applying a hash function, an output of each said XOR reduction tree generating said memory storage structure select signal.

6. The programmable memory system as claimed in claim 1, wherein each said one or more associated first logic device is responsive to pre-determined physical memory address bit locations having bit values used in generating said select signal for enabling even distribution of accesses across said one or more memory storage structures.

7. The programmable memory system as claimed in claim 1, wherein each said one or more associated first logic device is responsive to other pre-determined physical memory address bit locations used for assigning a memory region in said one or more memory structures to one or more processors.

8. The programmable memory system as claimed in claim 1, wherein said one or more memory storage structures comprises a single cache memory system, a multi-level memory system or a main memory storage system for a processor device.

9. A method for accessing a shared memory provided in a computing system having one or more processor devices, said shared memory organized as a plurality of memory storage structures having addressable locations for storing data for said one or more processor devices, said method comprising:

receiving, at a first logic device associated with each one or more processor devices, physical memory address bits and selecting bit values at pre-determined bit address locations of said received physical memory address signal;

generating, at said first logic device, a respective select signal corresponding to one of said plurality of memory storage structures based upon said pre-determined address bit values selected; and

,

generating, at a second logic device, in response to a corresponding select signal, an address signal used for selecting a memory storage structure for a processor device access, wherein each processor device of said computing system is enabled memory storage access distributed across said plurality of memory storage structures, and,

using unselected bit values of said received physical memory address signal to enable processor device access to memory locations within a selected memory storage structure

wherein each said respective select signal comprises an asserted bit value output,

said second logic device for concatenating one or more said asserted bit value outputs from each said associated first logic devices and generating a bit vector for use as said address signal.

10. The method as claimed in claim 9, further comprising:

programming said first logic device to provide a single processor device exclusive access to a single memory storage structure upon receipt of predetermined selected address bit values at pre-determined physical memory address bit locations.

11. The method as claimed in claim 9, further comprising:

programming each said one or more first logic devices to respond to pre-determined physical memory address bit locations used in generating said respective select signal for providing a single processor device with even distribution of accesses across said one or more memory storage structures.

12. The method as claimed in claim 9, further comprising:

programming said first logic device to respond to other pre-determined physical memory address bit locations used for assigning a memory region in said one or more memory structures to one or more processors.

13. A multiprocessor computing system comprising one or more processor devices and a shared memory comprising one or more memory storage structures having addressable locations for storing data for said one or more processor devices, said system comprising:

one or more first logic devices associated with a respective said one or more processor devices, each first logic device for receiving physical memory address bits, and each one or more first logic devices programmed to generate a respective select signal corresponding to one of said one or more memory storage structures upon receipt of address bit values at pre-determined physical memory address bit locations;

a second logic device responsive to said corresponding respective select signal for generating an address signal used for selecting a memory storage structure for processor access, wherein each processor device of said computing system enables memory storage access distributed across said one or more memory storage structures,

wherein unselected bit values of said received physical memory address bits are used to enable processor device access to memory locations within a selected memory storage structure, and,

wherein each said one or more associated first logic device output select signal comprises an asserted bit value output,

said second logic device for concatenating one or more said asserted bit value outputs from said one or more associated first logic devices and generating a bit vector for use as said address signal used to select a memory storage structure.

14. The multiprocessor computing system as claimed in claim 13, wherein said address bit values at said pre-determined physical memory address bit locations enable a single processor exclusive access to a single memory storage structure.

15. The multiprocessor computing system as claimed in claim 13, wherein each said one or more associated first logic device includes a multiplexer device programmed to respond to said address bit values at pre-determined physical memory address bit locations.

16. The multiprocessor computing system as claimed in claim 13, wherein each said one or more associated first logic device implements logic for applying a hash function to said physical memory address bits.

17. The multiprocessor computing memory system as claimed in claim 16, wherein each said one or more associated first logic device comprises an XOR reduction tree for applying a hash function, an output of each said XOR reduction tree generating said memory storage structure select signal.

18. An apparatus for enabling one or more processor devices access to shared memory in a computing system, the shared memory including one or more memory storage structures having addressable locations for storing data, said apparatus comprising:

one or more first logic devices associated with a respective processor device that provides a physical memory address, each said one or more first logic device for receiving a different subset of address bit signals comprising said physical memory address;

gating means associated with each said one or more first logic devices and each programmable for gating off some or all selected bits of each different subset of address bit signals received at each said respective said one or more first logic devices, wherein remaining ungated bits correspond to a desired shared memory storage structure to be accessed, each respective said one or more first logic devices receiving said remaining ungated bits for applying a hash function to said remaining ungated bits and generating a respective memory storage structure select signal; and

,

a second logic device responsive to each the respective select signal for generating an address signal used for selecting a memory storage structure for processor access, each respective select signal comprising a single output bit, said second logic device for concatenating one or more said single bit outputs from respective said one or more associated first logic devices to generate a bit vector for use as said address signal used to select a memory storage structure, whereby each processor device of a computing environment enables memory storage access distributed across the one or more memory storage structures.

19. The apparatus as claimed in claim 18, wherein each said one or more associated first logic devices comprises an XOR reduction tree for applying said hash function, an output of each said XOR reduction tree comprising said generated memory storage structure select signal.

20. The apparatus as claimed in claim 19, wherein each said gating means associated with each said one or more first logic devices comprises a column of logic gates receiving a respective different subset of address bit signals and receiving a control signal for controlling gating off said some or all selected bits.

21. The apparatus as claimed in claim 20, wherein each said logic gates include an AND gate.

22. The apparatus as claimed in claim 18, further comprising:

a means for receiving unselected or gated off bit values of each different subset of address bit signals of the received physical memory address and for generating an offset bit vector signal used to access memory locations within a selected memory storage structure.

23. A method for enabling one or more processor devices access to shared memory in a computing system, the shared memory including one or more memory storage structures having addressable locations for storing data, said method comprising:

receiving, at one or more first logic devices associated with a respective processor device that provides a physical memory addresses, a different subset of address bit signals comprising said physical memory address;

gating some or all selected bits of each different subset of address bit signals received at each said first logic device, wherein remaining ungated bits correspond to a desired shared memory storage structure to be accessed,

applying, at said one or more first logic devices, a hash function to said remaining ungated bits and generating a respective memory storage structure select signal; and

,

generating, at a second logic device, in response to a corresponding select signal, an address signal used for selecting a memory storage structure for a processor device access, each respective select signal comprising a single output bit, said second logic device for concatenating one or more said single bit outputs from respective said one or more associated first logic devices to generate a bit vector for use as said address signal used to select a memory storage structure,

wherein each processor device of said computing system is enabled memory storage access distributed across said one or more memory storage structures.

24. The method as claimed in claim 23, wherein each said one or more associated first logic devices comprises an XOR reduction tree for applying said hash function, an output of each said XOR reduction tree comprising said generated memory storage structure select signal.

25. The method as claimed in claim 23, further comprising:

receiving at a control signal for controlling gating of said some or all selected bits at said each associated said one or more first logic devices.

26. The method as claimed in claim 23, further comprising:

using unselected or gated off bit values of each different subset of address bit signals of the received physical memory address to enable processor device access to memory locations within a selected memory storage structure.