Interface for a semiconductor memory device and method for controlling the interface

• US 7,793,039 B2
• Filed: 01/06/2009
• Issued: 09/07/2010
• Est. Priority Date: 10/10/1997
• Status: Expired due to Fees

• Current Assignee: Rambus Inc.
• Original Assignee: Rambus Inc.
• Inventors: Gasbarro, James A., Barth, Richard M., Nguyen, David, Hampel, Craig E., Stark, Donald C., Ware, Frederick A., Davis, Paul G., Abhyankar, Abhijit M.
• Primary Examiner(s): BATAILLE, PIERRE MICHE
• Application Number:
  US12/349,485
• Publication Number:
  US 20090129178A1
• Time in Patent Office: 609 Days
• Field of Search: 711/111, 711/105, 711/167, 711/154
• US Class Current: 711/105
• CPC Class Codes: G11C 11/406 Management or control of the refreshing or charge-regeneration cycles
• CPC Class Codes: G11C 11/40611 External triggering or timing of internal or partially internal refresh operations, e.g. auto-refresh or CAS-before-RAS triggered refresh
• CPC Class Codes: G11C 11/4076 Timing circuits for regeneration management G11C11/406
• CPC Class Codes: G11C 11/4093 Input/output [I/O] data interface arrangements, e.g. data buffers
• CPC Class Codes: G11C 11/4096 Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
• CPC Class Codes: G11C 2207/2218 Late write
• CPC Class Codes: G11C 7/1006 Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
• CPC Class Codes: G11C 7/12 Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
• CPC Class Codes: G11C 8/12 Group selection circuits, e.g. for memory block selection, chip selection, array selection
• CPC Class Codes: G11C 8/18 Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals

Abstract

A semiconductor memory device includes a memory core, a first interface to receive write data from a first set of interconnect resources, and a second interface, separate from the first interface, to receive from a second set of interconnect resources a column address and a first code. The column address is associated with the write data and identifies a column of the memory core in which to store the write data. The first code indicates whether the write data is selectively masked by data mask information. If the first code indicates that the write data is selectively masked, the second interface is to receive data mask information specifying whether to selectively write portions of the write data to the memory core.

Claims

1. A semiconductor memory device comprising:

a memory core;

a first interface to receive write data from a first set of interconnect resources; and

a second interface, separate from the first interface, the second interface to receive from a second set of interconnect resources;

a column address associated with the write data, wherein the column address identifies a column of the memory core in which to store the write data; and

a first code indicating whether the write data is selectively masked by data mask information, and

wherein, if the first code indicates that the write data is selectively masked, the second interface is to receive data mask information specifying whether to selectively write portions of the write data to the memory core.

2. The semiconductor memory device of claim 1, wherein the second interface is to receive, prior to receiving the column address, a first bit which specifies whether precharging is to occur after the write data is written to the memory core.

3. The semiconductor memory device of claim 2, wherein the second interface is to receive, at the same time that it receives the first bit, a second code that specifies a write operation associated with the write data.

4. The semiconductor memory device of claim 3, wherein the second interface is to receive a bank address specifying a bank of the memory core for the write operation.

5. The semiconductor memory device of claim 4, wherein prior to receiving the column address and the write data, the memory device is to activate a row of the memory core in response to a row activation command, wherein the write data is to be written to the row in connection with the write operation, wherein the column address identifies a column in the row and wherein the row is located in the bank specified by the bank address.

6. The semiconductor memory device of claim 5, further comprising:

an input to receive a clock signal; and

a set of pins to receive a row address that identifies the row of the memory core, wherein for at least one pin of the set of pins, two bits of the row address are received during a clock cycle of the clock signal.

7. The semiconductor memory device of claim 6, wherein the set of pins are included in a third interface that is separate from the first interface and second interface.

8. The semiconductor memory device of claim 1, further comprising an input to receive a clock signal, wherein the first interface comprises a set of pins to receive the write data, wherein for every pin of the set of pins, eight bits of the write data are to be received in succession during four clock cycles of the clock signal.

9. The semiconductor memory device of claim 1, further comprising a third interface, separate from the first interface and the second interface, to receive a row activation command to activate a row of the memory core, wherein the write data is to be written to the row.

10. The semiconductor memory device of claim 9, wherein:

the first interface includes eighteen pins to receive the write data from the first set of interconnect resources, which consists of a data bus that has eighteen signal lines;

the second interface includes five pins to attach to the second set of interconnect resources, which consists of five signal lines; and

the third interface includes three pins to attach to a primary interconnect consisting of three signal lines.

11. A method for controlling a memory device having a memory core, the method comprising:

over a first set of interconnect resources, conveying write data associated with a write operation to the memory device; and

over a second set of interconnect resources that are separate from the first set of interconnect resources;

conveying a column address that identifies a column of the memory core associated with the write operation;

conveying a first code that specifies whether data mask information will be issued in connection with the write operation; and

if the first code specifies that the data mask information will be issued, then conveying the data mask information after conveying the first code, wherein the data mask information specifies whether to selectively write portions of the write data to the memory core.

12. The method of claim 11, wherein conveying the data mask information comprises conveying, over a signal line, two bits of the mask information during a clock cycle of a clock signal that is received by the memory device.

13. The method of claim 11, further comprising, over the second set of interconnect resources, conveying a bit which specifies whether precharging occurs after the write data is written to the memory core.

14. The method of claim 13, further comprising, conveying a column command specifying the write operation.

15. The method of claim 14, further comprising, prior to conveying the column command, conveying a row command that specifies activation of a row of the memory core, wherein the write data is to be written to the row in connection with the write operation, wherein the column is contained in the row.

16. The method of claim 15, wherein the row command is conveyed over a third set of interconnect resources in a first packet format, and the column command is conveyed over the second set of interconnect resources using a second packet format, wherein the third set of interconnect resources are separate from the first and second set of interconnect resources.

17. The method of claim 16, wherein the third set of interconnect resources is a primary interconnect consisting of three signal lines, the second set of interconnect resources is a secondary interconnect consisting of five signal lines, and the first set of interconnect resources is a data bus consisting of eighteen signal lines.

18. A method of controlling a memory device having a plurality of banks, the method comprising:

conveying a row command and a first bank address to activate a row in a bank identified by the first bank address;

conveying a column command and a second bank address, the column command specifying a write operation of write data to a bank identified by the second bank address;

conveying a column address that identifies a column associated with the write operation;

conveying a first code which specifies whether data mask information will be issued in connection with the write operation;

if the first code specifies that the data mask information will be conveyed, then conveying the data mask information after conveying the first code, the data mask information specifying whether to selectively write portions of write data to the memory core;

conveying a first bit which specifies whether precharging occurs after the write data is written to the memory core; and

conveying the write data associated with the write operation, wherein the write data is conveyed over signal lines separate from those used to convey the row command, first bank address, column command, second bank address, the first code and the first bit.

19. The method of claim 18, wherein the row command and first bank address are conveyed as a first packet over a first set of interconnect resources, and the column command, the column address, the first bit, and the first code are conveyed as a second packet over a second set of interconnect resources.

20. The method of claim 19, wherein the first set of interconnect resources is a primary interconnect consisting of three signal lines, and the second set of interconnect resources is a secondary interconnect consisting of five signal lines.

21. The method of claim 18, wherein both a bit of the second bank address and a bit of the column address are conveyed over a common signal line during a clock cycle of a clock signal.

22. The method of claim 21, wherein the first code and first bit are conveyed synchronously with respect to a first transition of the clock signal.

23. The method of claim 22, wherein conveying the data mask information comprises conveying, on a signal line, two bits of the data mask information during a clock cycle of the clock signal.

24. The method of claim 22, wherein the column address and the data mask information are conveyed synchronously with respect to transitions of the clock signal which succeed the first transition of the clock signal.

25. The method of claim 18, wherein the first bank address and the second bank address identify the same bank of the plurality of banks, such that the column address identifies a column of the row activated in the bank identified by both the first and second bank address.

26. The method of claim 18, wherein the first bank address identifies a first bank of the plurality of banks and the second bank address identifies a second bank of the plurality of banks, wherein the first bank and second bank are different banks.

27. The method of claim 26, wherein the row command and the first bank address are conveyed over a first set of interconnect resources during a time in which the column command, the column address, the second bank address, the first bit, and the first code are conveyed over a second set of interconnect resources, wherein the first set of interconnect resources is separate from the second set of interconnect resources.

28. A method of operation of a memory controller that controls a memory device, wherein the memory device receives a write command synchronously with respect to a clock signal to store write data associated with a write operation in a memory core of the memory device, the method comprising:

conveying, on a first signal line, a first code that specifies whether data mask information will be issued in connection with the write operation, wherein the first code is conveyed synchronously with respect to a first transition of the clock signal;

conveying, on a second signal line, precharge information that specifies whether precharging occurs after the write data is written to the memory core, wherein the precharge information is conveyed synchronously with respect to the first transition of the clock signal;

conveying column address information associated with the write operation, wherein a portion of the column address information is conveyed on the first and the second signal lines synchronously with respect to transitions of the clock signal that succeed the first transition of the clock signal;

conveying the write data over a set of lines that are separate from the first signal line and the second signal line; and

if the first code specifies that the data mask information will be issued, then conveying the data mask information to specify whether to selectively write portions of the write data to the memory core, wherein at least a portion of the data mask information is conveyed on the first signal line and the second signal line synchronously with respect to transitions of the clock signal that succeed the first transition of the clock signal.

29. The method of claim 28, wherein conveying the data mask information comprises conveying two bits of the data mask information over the first signal line during a clock cycle of the clock signal.

30. The method of claim 28, further comprising conveying a second code that specifies the write command to the memory device.

31. The method of claim 28, further comprising:

conveying the write command; and

prior to conveying the write command, conveying a row command that specifies activation of a row of the memory core, wherein the column is contained in the row, wherein the write data is to be written to the row in connection with the write operation.

32. The method of claim 31, wherein the row command is conveyed over a primary interconnect that is separate from the first signal line and the second signal line, and wherein the write command is conveyed over a secondary interconnect.

33. The method of claim 32, wherein the row command conveyed over the primary interconnect is included in a first packet format and the write command conveyed over the secondary interconnect is included in a second packet format.

34. The method of claim 32, wherein the primary interconnect consists of three signal lines, and the secondary interconnect consists of five signal lines.