Integrated circuit having frequency dependent noise avoidance

• US 7,793,132 B2
• Filed: 07/26/2006
• Issued: 09/07/2010
• Est. Priority Date: 07/26/2006
• Status: Expired due to Fees

• Current Assignee: Avago Technologies General IP PTE Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Rofougaran, Ahmadreza (Reza)
• Primary Examiner(s): Stoynov; Stefan
• Application Number:
  US11/494,147
• Publication Number:
  US 20080028248A1
• Time in Patent Office: 1,504 Days
• Field of Search: 713/500, 713/600, 331/1.R, 331/46, 326/93, 327/100, 375/316, 375/354, 455/130
• US Class Current: 713/500
• CPC Class Codes: H04B 15/06 by local oscillators of receivers

Abstract

An integrated circuit includes first, second and third circuits, a clock module and a rate adapting module. The first circuit causes frequency dependent noise and is clocked based on a clock signal. The second circuit is rate dependent and is clocked based on an operation dependent clock signal. The third circuit is susceptible to adverse performance when the frequency dependent noise has a component within a given frequency range. The clock module generates a clock signal having a rate such that frequency dependent noise components associated with the clock signal are outside the given frequency range. The rate adapting module is coupled to produce the operation dependent clock signal from the clock signal.

Claims

1. An integrated circuit comprises:

a first circuit that causes frequency dependent noise, wherein the first circuit is clocked based on a clock signal;

a second circuit that is rate dependent, wherein the second circuit is clocked based on an operation dependent clock signal;

a third circuit that is susceptible to adverse performance when the frequency dependent noise has a component within a given frequency range;

a clock module that generates a clock signal having the rate such that frequency dependent noise components associated with the clock signal are outside the given frequency range; and

a rate adapting module coupled to produce the operation dependent clock signal from the clock signal.

2. The integrated circuit of claim 1, wherein the frequency dependent noise comprises at least one of:

harmonic signal components;

spurs; and

digital noise.

3. The integrated circuit of claim 1 comprises:

the first circuit including an analog to digital converter, wherein a digital portion of the analog to digital converter is clocked based on the clock signal;

the second circuit including a baseband processing module, wherein the second circuit is clocked based on the operation dependent clock signal; and

the third circuit including a low noise amplifier.

4. The integrated circuit of claim 1, wherein the rate adapting module comprises at least one of:

a fractional-N frequency synthesizer;

direct digital frequency synthesizer;

a phase locked loop; and

digital logic circuitry.

5. The integrated circuit of claim 1, wherein the rate adapting module functions to:

establish an adjustment factor based on the rate dependency of the second circuit and the clock signal; and

adjust the rate of the clock signal based on the adjustment factor to produce the operation dependent clock signal.

6. The integrated circuit of claim 1, wherein the clock module functions to:

for an initial rate of the clock signal, determine whether the frequency dependent noise components are within the given frequency range; and

when the frequency dependent noise components are within the given frequency range, adjust the rate of the clock signal such that the frequency dependent noise components associated with the clock signal are outside the given frequency range.

7. An integrated circuit comprises:

a first circuit that causes frequency dependent noise, wherein the first circuit is clocked based on an adjusted clock signal;

a second circuit that is rate dependent, wherein the second circuit is clocked based on a clock signal;

a third circuit that is susceptible to adverse performance when the frequency dependent noise has a component within a given frequency range;

a clock source that generates a clock signal; and

the rate adapting module coupled to produce the adjusted clock signal from the clock signal such that frequency dependent noise components associated with the adjusted clock signal are outside the given frequency range.

8. The integrated circuit of claim 7, wherein the frequency dependent noise comprises at least one of:

harmonic signal components;

spurs; and

digital noise.

9. The integrated circuit of claim 7 comprises:

the first circuit including an analog to digital converter, wherein a digital portion of the analog to digital converter is clocked based on the clock signal;

the second circuit including a baseband processing module, wherein the second circuit is clocked based on the rate dependent clock signal; and

the third circuit including a low noise amplifier.

10. The integrated circuit of claim 7, wherein the rate adapting module comprises at least one of:

a fractional-N frequency synthesizer;

direct digital frequency synthesizer;

a phase locked loop; and

digital logic circuitry.

11. The integrated circuit of claim 7, wherein the rate adapting module functions to:

establish an adjustment factor based on the given frequency range and the clock signal; and

adjust the rate of the clock signal based on the adjustment factor to produce the adjusted clock signal.

12. The integrated circuit of claim 7, wherein the rate adapting module functions to:

determine whether the frequency dependent noise components are within the given frequency range; and

when the frequency dependent noise components are within the given frequency range, adjust a rate of the adjusted clock signal such that the frequency dependent noise components associated with the clock signal are outside the given frequency range.

13. A radio frequency integrated circuit (RFIC) comprises:

a low noise amplifier coupled to amplify an inbound radio frequency (RF) signal to produce an amplified RF signal;

down conversion module coupled to convert the amplified RF signal to a down converted signal based on a local oscillation;

analog to digital conversion (ADC) module coupled to convert the down converted signal into a digital signal, wherein the ADC conversion module is clocked by a first clock signal;

baseband processing module coupled to convert the digital signal into inbound data, wherein at least one function of the baseband processing module is clocked by an operation dependent clock signal; and

clock module coupled to produce the first clock signal and the operation dependent clock signal, wherein a rate of the first clock signal is set such that frequency dependent noise components associated with the first clock signal are outside a frequency band associated with the inbound RF signal and wherein a rate of the operation dependent clock signal is set based on processing specifications of the digital signal.

14. The RFIC of claim 13, wherein the clock module comprises:

a clock source that generates the first clock signal; and

a rate adjusting module that generates the operation dependent clock signal from the first clock signal.

15. The RFIC of claim 13, wherein the clock module comprises:

a clock source that generates the operation dependent clock signal; and

a rate adjusting module that generates the first clock signal from the operation dependent clock signal.

16. The RFIC of claim 13, wherein the at least one function of the baseband processing module comprises at least one of:

intermediate frequency to baseband conversion;

fast Fourier transform;

demapping;

deinterleaving;

decoding; and

descrambling.

17. The RFIC of claim 13, wherein the down conversion module comprises:

a local oscillation module coupled to generate the local oscillation based on the operation dependent clock signal;

mixing module coupled to mix the local oscillation with the amplified RF signal to produce first and second mixed signals; and

filtering module coupled to filter the first and second mixed signals to produce an in-phase component and a quadrature component of the down converted signal.