Semiconductor apparatus and test method therefor

• US 7,793,174 B2
• Filed: 03/16/2007
• Issued: 09/07/2010
• Est. Priority Date: 03/22/2006
• Status: Expired due to Fees

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: NEC Electronics Corporation (Renesas Electronics Corporation)
• Inventors: Hattori, Takashi, Ikeda, Kouji, Hashidume, Yumiko, Nishino, Tatsuhiro
• Primary Examiner(s): Gaffin; Jeffrey A
• Assistant Examiner(s): Merant; Guerrier
• Application Number:
  US11/723,140
• Publication Number:
  US 20070245200A1
• Time in Patent Office: 1,271 Days
• Field of Search: None
• US Class Current: 714/718
• CPC Class Codes: G11C 2029/0401 in embedded memories
• CPC Class Codes: G11C 29/028 with adaption or trimming of parameters
• CPC Class Codes: G11C 29/16 using microprogrammed units, e.g. state machines
• CPC Class Codes: G11C 29/36 Data generation devices, e.g. data inverters
• CPC Class Codes: G11C 29/50012 of timing

Abstract

A SiP includes a logic chip and a memory chip. The memory chip includes a memory circuit to be tested, and the logic chip includes an internal logic circuit and a test processor electrically connected therewith. The test processor is connected with an access terminal of the memory circuit and supplies a test signal input from an external terminal to the access terminal to thereby test the memory circuit. The test processor includes a high-speed test control circuit to adjust signal delay and supplies a test signal from the external terminal to the access terminal through the high-speed test control circuit when performing high-speed test at an actual operation speed.

Claims

1. A semiconductor apparatus comprising:

a memory chip including a memory circuit to be tested; and

a logic chip including an internal logic circuit and a test processor connected with the internal logic circuit and the memory circuit to access the memory circuit through an external terminal and test the memory circuit, the test processor including a high-speed test control circuit capable of selecting a signal transfer rate between the external terminal and the memory circuit according to a test speed when testing the memory circuit,

wherein the high-speed test control circuit includes a high-speed test adjustment circuit to set the signal transfer rate to a desired signal transfer rate when the test processor performs high-speed test at an actual operation speed, and

wherein the high-speed test adjustment circuit includes a plurality of stages of flip-flops which passes through a test signal between the memory chip and the logic chip.

2. The semiconductor apparatus according to claim 1,

wherein the high-speed test control circuit selects a lower signal transfer rate than an actual operation speed when the test processor performs low-speed test at a lower speed than an actual operation speed.

3. The semiconductor apparatus according to claim 2,

wherein the test processor comprises a first selector to receive a test signal from the external terminal at one input and a test signal through the high-speed test adjustment circuit at another input and to selectively output either one of the test signals according to a test speed selection signal to select one of high-speed test mode and low-speed test mode.

4. The semiconductor apparatus according to claim 2,

wherein the test processor comprises a second selector to receive a test signal at one input and a user signal from the internal logic circuit at another input and to selectively output either one of the signals according to a mode selection signal to select one of test mode and user mode.

5. The semiconductor apparatus according to claim 1,

wherein the test processor comprises a first selector to receive a test signal from the external terminal at one input and a test signal through the high-speed test adjustment circuit at another input and to selectively output either one of the test signals according to a test speed selection signal to select one of high-speed test mode and low-speed test mode.

6. The semiconductor apparatus according to claim 1,

wherein the test processor comprises a second selector to receive a test signal at one input and a user signal from the internal logic circuit at another input and to selectively output either one of the signals according to a mode selection signal to select one of test mode and user mode.

7. The semiconductor apparatus according to claim 1, comprising

a plurality of memory chips connected with the logic chip,

wherein the test processor of the logic chip independently tests memory circuits of the plurality of memory chips.

8. The semiconductor apparatus according to claim 1, comprising:

a plurality of test processors in the logic chip; and

a plurality of memory chips corresponding one to one with the plurality of the test processors.

9. A test method of a semiconductor apparatus comprising:

supplying a test signal from an external terminal through a high-speed test control circuit included in a test processor connected with an internal logic circuit on a logic chip and capable of selecting a signal transfer rate between the external terminal and a memory circuit to be tested on a memory chip according to a test speed; and

performing test on the memory circuit.

wherein when the test processor conducts high-speed test at an actual operation speed, the high-speed test is performed using a high-speed test adjustment circuit in the high-speed test control circuit by setting the signal transfer rate between the external terminal and the memory circuit to a desired signal transfer rate, by passing through the test signal in a plurality of stages of flip-flops in the high-speed test adjustment circuit.

10. The test method of a semiconductor apparatus according to claim 9, wherein

when the test processor conducts low-speed test at a lower speed than an actual operation speed, the low-speed test is performed by the high-speed test control circuit by setting the signal transfer rate between the external terminal and the memory circuit to a lower signal transfer rate than the actual operation speed.

11. A semiconductor apparatus, comprising:

a memory chip;

a test terminal which receives a first signal including a data signal, an address signal, a control signal and a clock signal in a test mode;

a logic circuit which outputs a second signal including a data signal, an address signal, a control signal and a clock signal in a user mode;

a first gate which transfers the first signal in the test mode;

a high test adjustment circuit which includes at least one flip-flop to latch the data signal, the address signal and the control signal of the first signal and output a latched signal latched in the flip-flop in response to the clock signal outputted from the first gate in the test mode;

a second gate which outputs an output of the first gate without intervening the high test adjustment circuit in a first test state of the test mode, and outputs the latched signal in a second test state of the test mode;

a third gate which transfers the first signal between the logic circuit and the memory chip in the user mode, and transfers an output of the second gate to the memory chip in the test mode, said third gate outputting the clock signal of the first signal and the clock signal of the second signal, without intervening the high test adjustment circuit, respectively in the user mode and the test mode.