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Semiconductor apparatus and test method therefor

  • US 7,793,174 B2
  • Filed: 03/16/2007
  • Issued: 09/07/2010
  • Est. Priority Date: 03/22/2006
  • Status: Expired due to Fees
First Claim
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1. A semiconductor apparatus comprising:

  • a memory chip including a memory circuit to be tested; and

    a logic chip including an internal logic circuit and a test processor connected with the internal logic circuit and the memory circuit to access the memory circuit through an external terminal and test the memory circuit, the test processor including a high-speed test control circuit capable of selecting a signal transfer rate between the external terminal and the memory circuit according to a test speed when testing the memory circuit,wherein the high-speed test control circuit includes a high-speed test adjustment circuit to set the signal transfer rate to a desired signal transfer rate when the test processor performs high-speed test at an actual operation speed, andwherein the high-speed test adjustment circuit includes a plurality of stages of flip-flops which passes through a test signal between the memory chip and the logic chip.

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