Resistance-based etch depth determination for SGT technology

• US 7,795,108 B2
• Filed: 03/06/2009
• Issued: 09/14/2010
• Est. Priority Date: 03/23/2007
• Status: Expired due to Fees

• Current Assignee: Alpha & Omega Semiconductor, Ltd.
• Original Assignee: Alpha & Omega Semiconductor, Ltd.
• Inventors: Lou, Yingying, Wang, Yu, Bhalla, Anup, Li, Tiesheng
• Primary Examiner(s): Garber; Charles D
• Assistant Examiner(s): STEVENSON, ANDRE C
• Application Number:
  US12/399,632
• Publication Number:
  US 20090166621A1
• Time in Patent Office: 557 Days
• Field of Search: None
• US Class Current: 438/426
• CPC Class Codes: H01L 22/12 for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions electrical measurement of diffusions H01L22/14
• CPC Class Codes: H01L 22/14 for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means
• CPC Class Codes: H01L 22/34 Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line switching, multiplexing, gating devices G01R19/25; process control with lithography, e.g. dose control, G03F7/20; structures for alignment control by optical means G03F7/70633
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A method for determining the depth etch, a method of forming a shielded gate trench (SGT) structure and a semiconductor device wafer are disclosed. A material layer is formed over part of a substrate having a trench. The material fills the trench. A resist mask is placed over a test portion of the material layer thereby defining a test structure that lies underneath the resist mask. The resist mask does not cover the trench. The material is isotropically etched and a signal related to a resistance change of the test structure is measured. A lateral undercut D_L of the test structure is determined from the signal and an etch depth D_T is determined from D_L. The wafer may comprise one or more test structures forming a bridge circuit; one or more metal contacts that electrically connect the test structures through contact holes: and resist layer including over the test structures.

Claims

1. A wafer of semiconductor field effect transistors comprising:

one or more polysilicon test structures forming a Wheatstone bridge circuit;

a layer of dielectric material including one or more portions that cover one or more corresponding portions of the test structures; and

one or more metal contacts configured to electrically connect the test structures through contact holes opened through the dielectric material covering the test structures,

wherein the polysilicon test structures form four polysilicon resistors at four arms of the Wheatstone bridge circuit.

2. The wafer of claim 1 wherein one or more of the test structures comprises a bar shape.

3. The wafer of claim 1, wherein the polysilicon resistors at two opposite arms of the Wheatstone bridge are identical.

4. The wafer of claim 1, wherein the four polysilicon resistors comprise two identical polysilicon resistors that are bigger than two other identical polysilicon resistors.

5. The wafer of claim 3 wherein a length to width ratio L/W of two identical polysilicon resistors is larger than a length to width ratio L/W of other two identical polysilicon resistors.