Method of fabricating self-aligned source and drain contacts in a double gate FET with controlled manufacturing of a thin Si or non-Si channel

• US 7,795,112 B2
• Filed: 03/28/2005
• Issued: 09/14/2010
• Est. Priority Date: 03/29/2004
• Status: Active Grant

• Current Assignee: NXP B.V. (NXP Semiconductors NV)
• Original Assignee: IMEC International, NXP B.V. (NXP Semiconductors NV)
• Inventors: Ponomarev, Youri V., Loo, Josine Johanna Gerarda Petra
• Primary Examiner(s): Coleman; W. David
• Assistant Examiner(s): CRAWFORD, LATANYA N
• Application Number:
  US11/093,265
• Publication Number:
  US 20050227444A1
• Time in Patent Office: 1,996 Days
• Field of Search: 257/9, 257/347, 257/349, 257/500, 257/401, 257/E21.421, 257/E29.264, 257/E21.568, 257/E21.569, 257/E29.295, 438/162, 438/286, 438/289, 438/459, 438/689, 438/285, 438/192, 438/165, 438/302, 438/370, 438/377, 438/310, 438/517, 438/977, 438/458, 451/285
• US Class Current: 438/458
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: H01L 21/26506 in group IV semiconductors
• CPC Class Codes: H01L 29/66575 where the source and drain or source and drain extensions are self-aligned to the sides of the gate H01L29/66606 takes precedence

Abstract

A method of forming a transistor structure on a substrate (SOI) is disclosed, wherein the substrate comprises a supporting Si layer, a buried insulating layer, and a top Si layer. The method comprises forming a gate region of the transistor structure on the top Si layer, wherein the gate region is separated from the top Si layer by a dielectric layer, and wherein the top Si layer comprises a high dopant level. The method further comprises forming an open area on the top Si layer demarcated by a demarcating oxide and/or resist layer region, forming high level impurity or heavily-damaged regions by ion implantation, and exposing the open area to an ion beam, wherein the ion beam comprises a combination of beam energy and dose, and wherein the demarcating layer region and the gate region act as an implantation mask.

Claims

1. A method of forming a transistor structure on a substrate comprising a supporting Si layer, a buried insulating layer, and a top Si layer, the method comprising:

forming a gate region of the transistor structure on the top Si layer, wherein the gate region is separated from the top Si layer by a dielectric layer, and wherein the top Si layer is doped;

forming open areas on the top Si layer demarcated by at least one of a demarcating oxide, a resist layer region, and the gate region;

exposing the transistor structure comprising the open areas to ion implantation through the gate region wherein the demarcating layer region and the gate region act as an implantation mask, so as to simultaneously form impurity regions below the open areas in the buried insulating layer and an impurity region below the gate region in the top Si layer, wherein the impurity region below the gate region has a higher impurity level than regions below the open areas in the top Si layer to allow a selective removal of the impurity region below the gate region relative to the regions below the open areas in the top Si layer; and

removing the impurity region in the top Si layer below the gate region by selective etching using the regions below the open areas in the top Si layer as a stopping layer, thereby creating a gap between the regions below the open areas in the top Si layer.

2. The method of forming a transistor structure according to claim 1, further comprising:

forming a silicon dioxide capping layer;

wafer bonding the substrate to a second substrate, wherein the second substrate comprises a silicon dioxide top layer, and wherein the capping layer is face-to-face with the silicon dioxide top layer.

3. The method of forming a transistor structure according to claim 1, further comprising:

initially removing the supporting Si layer using the buried insulating layer as a stopping layer;

further removing the buried insulating layer using the top Si layer as a stopping layer.

4. The method of forming a transistor structure according to claim 1, further comprising using one of the dielectric region and the gate region as an additional stopping layer for removing the impurity region of the top Si layer below the gate region.

5. The method of forming a transistor structure according to claim 1, further comprising depositing a channel layer in the gap to form a channel region.

6. The method of forming a transistor structure according to claim 1, wherein the ion beam comprises ions of one of Ge, I, and Br.

7. The method of forming a transistor structure according claim 1, wherein the transistor structure is a MOSFET structure.

8. A transistor structure on a substrate, comprising a gate region, and a source and drain region, wherein the transistor structure is fabricated according to the method of claim 1.

9. The method of claim 1, wherein the ion implantation is performed at an angle substantially perpendicular to the top Si layer.

10. The method of claim 1, wherein the impurity region below the gate region in the top Si layer extends over substantially the whole area in the top Si layer below the gate region.

11. The method of claim 1, wherein the impurity regions below the open areas in the buried insulating layer and the impurity region below the gate region in the top Si layer are formed in the same ion implantation process.

12. The method of forming a transistor structure according to claim 5, wherein the channel layer comprises as channel material at least one of the following:

a semiconductor material including one of Si, SiGe, Ge, GaAs, and InP, a III-V compound, a II-VI compound, a metal, an intermetallic compound, an organic compound, and a bio-organic compound.

13. The method of forming a transistor structure according to claim 5, wherein the channel layer comprises one of a quantum wire structure and a quantum dot structure.

14. The method of forming a transistor structure according to claim 13, wherein the channel layer comprises one of nano-wires, an array of nano-dots, carbon nano-dots, and nano-tubes.

15. A semiconductor device comprising a transistor structure in accordance with claim 8.

16. A method of forming a transistor structure on a substrate comprising a supporting Si layer, a buried insulating layer, and a top Si layer, the method comprising:

forming an emitter region of the transistor structure on the top Si layer, wherein the emitter region is separated from the top Si layer by a base layer, and wherein the top Si layer is doped;

forming open areas on the top Si layer demarcated by at least one of a demarcating oxide, a resist layer region, and the emitter region;

exposing the transistor structure comprising the open areas to ion implantation through the emitter region wherein the demarcating layer region and the emitter region act as an implantation mask so as to simultaneously form impurity regions below the open areas in the buried insulating layer and an impurity region below the emitter region in the top Si layer, wherein the impurity region below the emitter region has a higher impurity level than regions below the open areas in the top Si layer to allow a selective removal of the impurity region below the emitter region relative to the regions below the open areas in the top Si layer; and

removing the impurity region in the top Si layer below the emitter region by selective etching using the regions below the open areas in the top Si layer as stopping layer, thereby creating a gap between the regions below the open areas in the top Si layer.

17. The method of claim 16, further comprising:

forming a silicon dioxide capping layer;

wafer bonding the substrate to a second substrate, wherein the second substrate comprises a silicon dioxide top layer, and wherein the capping layer is face-to-face with the silicon dioxide top layer.

18. The method of claim 16, further comprising:

initially removing the supporting Si layer using the buried insulating layer as a stopping layer;

further removing the buried insulating layer using the top Si layer as a stopping layer.

19. The method of claim 16, further comprising:

depositing a collector layer in the gap to form a collector region.

20. The method of claim 16, wherein the ion implantation is performed at an angle substantially perpendicular to the top Si layer.

21. The method of claim 16, wherein the impurity regions below the open areas in the buried insulating layer and the impurity region below the emitter region in the top Si layer are formed in the same ion implantation process.

22. The method of claim 16, wherein the impurity region below the emitter region in the top Si layer extends over substantially the whole area in the top Si layer below the emitter region.