Method of manufacturing semiconductor device

• US 7,795,115 B2
• Filed: 12/27/2006
• Issued: 09/14/2010
• Est. Priority Date: 12/28/2005
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Sanyo Semiconductor Company Limited (ON Semiconductor Corporation), SANYO Semiconductor Manufacturing Co., Ltd. (ON Semiconductor Corporation), Sanyo Electric Company Limited (Panasonic Holdings Corporation)
• Inventors: Kameyama, Koujiro, Oikawa, Takahiro, Suzuki, Akira
• Primary Examiner(s): Booth; Richard A.
• Application Number:
  US11/645,811
• Publication Number:
  US 20070166957A1
• Time in Patent Office: 1,357 Days
• Field of Search: 438460-464, 438/667
• US Class Current: 438/460
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 21/78 with subsequent division of the substrate into plural individual devices cutting to change the surface-physical characteristics or shape of semiconductor bodies H01L21/304
• CPC Class Codes: H01L 2224/02372 connecting to a via connection in the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/03002 for supporting the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05009 Bonding area integrally formed with a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05548 Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/06181 On opposite sides of the body
• CPC Class Codes: H01L 2224/11002 for supporting the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/13022 the bump connector being at least partially embedded in the surface
• CPC Class Codes: H01L 2224/13024 the bump connector being disposed on a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 2924/09701 Low temperature co-fired ceramic [LTCC]

Abstract

The invention is directed to enhancement of reliability and a yield of a semiconductor device by a method of manufacturing the semiconductor device with a supporting body without making the process complex. A second insulation film, a semiconductor substrate, a first insulation film, and a passivation film are etched and removed in this order using a resist layer or a protection layer as a mask. By this etching, an adhesive layer is partially exposed in an opening. At this time, a number of semiconductor devices are separated in individual semiconductor dies. Then, as shown in FIG. 10, a solvent (e.g. alcohol or acetone) is supplied to the exposed adhesive layer through the opening to gradually reduce its adhesion and thereby a supporting body is removed from the semiconductor substrate.

Claims

1. A method of manufacturing a semiconductor device, comprising:

forming a groove in a semiconductor substrate from a front surface thereof;

attaching a supporting body to the front surface of the semiconductor substrate having the groove formed therein using an adhesive layer disposed between the supporting body and the front surface of the semiconductor substrate, the adhesive layer filling the groove in the semiconductor substrate at least partially;

forming an opening in the semiconductor substrate from a back surface thereof so that the opening is connected with the groove to expose a portion of the adhesive layer; and

separating the supporting body from the semiconductor substrate by supplying a solvent to the exposed portion of the adhesive layer so as to dissolve the adhesive layer.

2. The method of claim 1, wherein the formation of an opening in the semiconductor is performed using a dicing blade, a laser or etching.

3. The method of claim 1, further comprising grinding the back surface of the semiconductor substrate after the attaching of the supporting body.

4. The method of claim 1, wherein the groove is formed along a dicing line of the semiconductor substrate.

5. The method of claim 1, wherein the groove is not formed in a periphery portion of the semiconductor substrate.

9. The method of claim 1, further comprising, after the attaching of the supporting body, forming a via hole in the semiconductor substrate from the back surface of the semiconductor substrate, forming a wiring layer in the via hole so as to extend over the back surface of the semiconductor substrate, and forming a protection film on the back surface of the semiconductor substrate to cover the wiring layer.

10. The method of claim 1, wherein the supporting body has no path for supplying the solvent.

11. The method of claim 1, wherein the supporting body comprises a rigid substrate.

6. A method of manufacturing a semiconductor device, comprising:

forming a groove in a semiconductor substrate from a front surface thereof;

forming an insulation film on the front surface of the semiconductor substrate and a pad electrode on the insulation film;

attaching a supporting body to the front surface of the semiconductor substrate having the groove, the insulation film and the pad electrode using an adhesive layer disposed between the supporting body and the front surface of the semiconductor substrate;

after the attaching of the supporting body, exposing the pad electrode by removing a portion of the semiconductor substrate and a portion of the insulation film from the back surface of the semiconductor substrate;

forming a wiring layer electrically connected with the exposed pad electrode;

forming a protection film on the back surface of the semiconductor substrate to cover the wiring layer;

forming an opening in the semiconductor substrate from a back surface thereof so that the opening is connected with the groove to expose a portion of the adhesive layer; and

separating the supporting body from the semiconductor substrate by supplying a solvent to the exposed portion of the adhesive layer so as to dissolve the adhesive layer.

7. The method of claim 6, further comprising forming an electrode connection layer on the pad electrode prior to the attaching of the supporting body, the electrode connection layer being configured for electrical connection with an electrode of an external semiconductor device.

8. The method of claim 7, wherein the electrode connection layer comprises nickel, gold, copper, tin or a combination thereof.

12. A method of manufacturing a semiconductor device, comprising:

forming a groove in a semiconductor substrate from a front surface thereof;

attaching a supporting body to the front surface of the semiconductor substrate having the groove formed therein using an adhesive layer disposed between the supporting body and the front surface of the semiconductor substrate, the adhesive layer filling the groove in the semiconductor substrate at least partially so as to be in direct contact with a sidewall of the groove;

thinning the semiconductor substrate by grinding a back surface of the semiconductor substrate so as to expose a portion of the adhesive layer; and

separating the supporting body from the semiconductor substrate by supplying a solvent to the exposed portion of the adhesive layer so as to dissolve the adhesive layer.

13. The method of claim 12, wherein the groove is formed along a dicing line of the semiconductor substrate.

14. The method of claim 12, wherein the groove is not formed in a periphery portion of the semiconductor substrate.

15. The method of claim 12, further comprising, prior to the attaching of the supporting body, forming an insulation film on the front surface of the semiconductor substrate and a pad electrode on the insulation film, and further comprising, after the attaching of the supporting body, exposing the pad electrode by removing a portion of the semiconductor substrate and a portion of the insulation film from the back surface of the semiconductor substrate, forming a wiring layer electrically connected with the exposed pad electrode, and forming a protection film on the back surface of the semiconductor substrate to cover the wiring layer.

16. The method of claim 15, further comprising forming an electrode connection layer on the pad electrode prior to the attaching of the supporting body, the electrode connection layer being configured for electrical connection with an electrode of an external semiconductor device.

17. The method of claim 16, wherein the electrode connection layer comprises nickel, gold, copper, tin or a combination thereof.

18. The method of claim 12, further comprising, after the attaching of the supporting body, forming a via hole in the semiconductor substrate from the back surface of the semiconductor substrate, forming a wiring layer in the via hole so as to extend over the back surface of the semiconductor substrate, and forming a protection film on the back surface of the semiconductor substrate to cover the wiring layer.

19. The method of claim 12, wherein the supporting body comprises a rigid substrate.