DRAM device and method of manufacturing the same
First Claim
1. A dynamic random access memory (DRAM) structure comprising:
- a multiple tunnel junction (MTJ) structure including conductive patterns and nonconductive patterns alternately stacked on each other, the nonconductive patterns having a band gap larger than a band gap of the conductive patterns;
a first insulation layer arranged on a sidewall of the MTJ structure;
a gate electrode arranged on the first insulation layer;
a word line electrically connected with the MTJ structure;
a bit line electrically connected with one of a top surface and a bottom surface of the MTJ structure; and
a capacitor electrically connected with one of a top surface and a bottom surface of the MTJ structure that is not connected with the bit line.
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Abstract
In a DRAM device and a method of manufacturing the same, a multiple tunnel junction (MTJ) structure is provided, which includes conductive patterns and nonconductive patterns alternately stacked on each other. The nonconductive patterns have a band gap larger than a band gap of the conductive patterns. A gate insulation layer and a gate electrode are formed on a sidewall of the MTJ structure. A word line is connected with the MTJ structure, and a bit line is connected with one of top and bottom surfaces of the MTJ structure. A capacitor is connected with one of top and bottom surfaces of the MTJ structure that is not connected with the bit line. Current leakage in the DRAM device is reduced and a unit cells may be vertically stacked on the substrate, so a smaller surface area of the substrate is required for the DRAM device.
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Citations
15 Claims
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1. A dynamic random access memory (DRAM) structure comprising:
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a multiple tunnel junction (MTJ) structure including conductive patterns and nonconductive patterns alternately stacked on each other, the nonconductive patterns having a band gap larger than a band gap of the conductive patterns; a first insulation layer arranged on a sidewall of the MTJ structure; a gate electrode arranged on the first insulation layer; a word line electrically connected with the MTJ structure; a bit line electrically connected with one of a top surface and a bottom surface of the MTJ structure; and a capacitor electrically connected with one of a top surface and a bottom surface of the MTJ structure that is not connected with the bit line. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15)
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Specification