Termination for trench MIS device

• US 7,795,675 B2
• Filed: 09/21/2005
• Issued: 09/14/2010
• Est. Priority Date: 03/26/2004
• Status: Active Grant

• Current Assignee: Siliconix Incorporated (Vishay Intertechnology Incorporated)
• Original Assignee: Siliconix Incorporated (Vishay Intertechnology Incorporated)
• Inventors: Qi, Jainhai, Terrill, Kyle W., Chen, Qufei, Darwish, Mohamed N.
• Primary Examiner(s): Gurley; Lynne A
• Assistant Examiner(s): Li; Meiya
• Application Number:
  US11/233,145
• Publication Number:
  US 20060011976A1
• Time in Patent Office: 1,819 Days
• Field of Search: 257/368, 257/E29.04, 257/E29.027, 257/341, 257329-331, 257/372, 257/376, 257/345, 257/396, 257397-400, 257/E29.066, 257/E29.133, 257/E29.146, 257/334, 438/268, 438/192, 438/212, 438/270
• US Class Current: 257/341
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A trench MIS device is formed in a P-epitaxial layer that overlies an N-epitaxial layer and an N+ substrate. In one embodiment, the device includes an N-type drain-drift region that extends from the bottom of the trench to the N-epitaxial layer. Preferably, the drain-drift region is formed at least in part by fabricating spacers on the sidewalls of the trench and implanting an N-type dopant between the sidewall spacers and through the bottom of the trench. The drain-drift region can be doped more heavily than the conventional “drift region” that is formed in an N-epitaxial layer. Thus, the device has a low on-resistance. The device can be terminated by a plurality of polysilicon-filled termination trenches located near the edge of the die, with the polysilicon in each termination trench being connected to the mesa adjacent the termination trench.

Claims

1. A semiconductor structure comprising a semiconductor die, said die comprising:

a first layer of a first conductivity type overlying a second layer of said first conductivity type, and a body region of a second conductivity type opposite to said first conductivity type overlying said first layer;

a plurality of trenches formed in said die, each of said trenches extending downward from a surface of said die through said body region and having a bottom located in said first layer;

said plurality of trenches comprising an active trench and a plurality of termination trenches, said plurality of termination trenches comprising a first termination trench and a second termination trench, said first termination trench being separated from said second termination trench by a first mesa, said second termination trench being separated from an edge of said die by a second mesa;

said structure further comprising;

an MIS device, said MIS device comprising;

said active trench, said active trench comprising a conductive gate material; and

a source region of said first conductivity type located adjacent said surface of said die and a sidewall of said active trench;

said structure further comprising a termination region, said termination region comprising;

said first and second termination trenches, each of said first and second termination trenches comprising a conductive material, said conductive material in each of said first and second termination trenches being separated from said body region and said first layer by a dielectric layer lining the bottom and sidewalls of each of said first and second termination trenches, said body region extending continuously across said first mesa;

a first short-circuit connection between said conductive material in said first termination trench and a first portion of said body region in said first mesa, and a second short-circuit connection between said conductive material in said second termination trench and a second portion of said body region in said second mesa, wherein there is no short-circuit connection between said conductive material in said second termination trench and said conductive material in said first termination trench or between said conductive material in said second termination trench and said first mesa.

2. The semiconductor structure of claim 1 wherein each of said first and second mesas comprises a heavily-doped contact region of said second conductivity type at said surface of said die, said structure further comprising a first metal layer in contact with the conductive material in said first termination trench and the heavily-doped contact region in said first mesa and a second metal layer in contact with the conductive material in said second termination trench and the heavily-doped contact region in said second mesa.

7. The semiconductor structure of claim 2 wherein the second metal layer does not contact the first mesa.

3. A semiconductor structure comprising a semiconductor die, the semiconductor structure further comprising:

an MIS device, the MIS device comprising a terminal adjacent a top side of the die; and

a termination region abutting an edge of the die, the termination region comprising;

a plurality of trenches, each of said trenches extending downward from said top side of the die through a body layer of a first conductivity and into a layer of a second conductivity type opposite to the first conductivity type, each of the trenches bordered by sidewalls and a bottom;

each of the trenches containing a conductive material, the conductive material in each trench being separated from the body layer and the layer of second conductivity type by a dielectric layer lining the sidewalls and bottom of the trench;

said trenches comprising a first trench separated from a second trench by a first mesa, said second trench being separated from the edge of the die by a second mesa; and

a first short-circuit connection between said conductive material in said first trench and a first portion of said body layer in said first mesa and a second short-circuit connection between said conductive material in said second trench and a second portion of said body region in said second mesa;

there being no short-circuit connection between said conductive material in said second trench and said first mesa and there being no short-circuit connection between said conductive material in either of said first and second trenches and said terminal.

4. The semiconductor structure of claim 3 wherein said MIS device comprises a MOSFET, said terminal comprises a source terminal and said layer of second conductivity type comprises a drain region.

5. The semiconductor structure of claim 4 wherein said MOSFET comprises an active trench, said active trench extending downward from said top side of the die through said body layer and into said layer of second conductivity type, and a source region adjacent said top side of said die and said active trench.

6. The semiconductor structure of claim 3 wherein said body region extends continuously across each of said first and second mesas.

8. The semiconductor structure of claim 3 wherein each of said first and second mesas comprises a heavily-doped contact region of said first conductivity type at said surface of said die, said structure further comprising a first metal layer in contact with the conductive material in said first termination trench and the heavily-doped contact region in said first mesa and a second metal layer in contact with the conductive material in said second termination trench and the heavily-doped contact region in said second mesa.

9. The semiconductor structure of claim 8 wherein the second metal layer does not contact the first mesa.

10. The semiconductor structure of claim 9 wherein neither of said first and second metal layers contacts said terminal.