Inductively coupled integrated circuit with magnetic communication path and methods for use therewith

• US 7,795,700 B2
• Filed: 02/28/2008
• Issued: 09/14/2010
• Est. Priority Date: 02/28/2008
• Status: Active Grant

• Current Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Rofougaran, Ahmadreza (Reza)
• Primary Examiner(s): CHU, CHRIS C
• Application Number:
  US12/039,256
• Publication Number:
  US 20090218701A1
• Time in Patent Office: 929 Days
• Field of Search: 257/E23.114, 257778-781, 257/783, 257/786, 257723-725, 257/277, 257/531, 257/904, 257/924, 257/E21.022, 438/108, 298/40, 219/121.63, 219/121.64
• US Class Current: 257/531
• CPC Class Codes: H01L 2225/06527 Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
• CPC Class Codes: H01L 23/645 Inductive arrangements H01L23/647, H01L23/66 take precedence
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/30107 Inductance
• CPC Class Codes: H01L 2924/3011 Impedance
• CPC Class Codes: H04B 5/263 Multiple coils at either side
• CPC Class Codes: H04B 5/266 One coil at each side, e.g. with primary and secondary coils
• CPC Class Codes: Y10S 257/904 with passive components,, e.g. polysilicon resistors
• CPC Class Codes: Y10S 257/924 with passive device, e.g. capacitor, or battery, as integral part of housing or housing element, e.g. cap

Abstract

An integrated circuit includes a first integrated circuit die having a first circuit and a first inductive interface and a second integrated circuit die having a second circuit and a second inductive interface. A substrate is coupled to support the first integrated circuit die and the second integrated circuit die, the substrate including a magnetic communication path aligned with the first inductive interface and the second inductive interface, to magnetically communicate signals between the first circuit and the second circuit.

Claims

1. An integrated circuit comprising:

a first integrated circuit die having a first circuit and a first inductive interface that includes a first coil; and

a second integrated circuit die having a second circuit and a second inductive interface that includes a second coil;

a substrate coupled to support the first integrated circuit die and the second integrated circuit die, the substrate including a magnetic communication path aligned with the first inductive interface and the second inductive interface, to magnetically communicate signals between the first circuit and the second circuit;

wherein the magnetic communication path includes a third coil aligned with the first coil and a fourth coil, coupled to the third coil and aligned with the second coil.

2. The integrated circuit of claim 1 wherein the first integrated circuit die is bonded to the substrate via a ferromagnetic glue.

3. The integrated circuit of claim 2 wherein the second integrated circuit die is bonded to the substrate via a ferromagnetic glue.

4. The integrated circuit of claim 1 wherein the third coil is planarly aligned with the first coil and the fourth coil is planarly aligned with the second coil.

5. The integrated circuit of claim 1 wherein the third coil is axially aligned with the first coil and the fourth coil is axially aligned with the second coil.

6. The integrated circuit of claim 1 wherein the magnetic communication path includes a ferromagnetic material.

7. The integrated circuit of claim 1 wherein the magnetic communication path is aligned to magnetically communicate signals bidirectionally between the first circuit and the second circuit.

8. The integrated circuit of claim 1 wherein the first integrated circuit die is stacked above the substrate and the second integrated circuit die is stacked below the substrate in a flip-chip configuration.

9. An integrated circuit comprising:

a first integrated circuit die having a first circuit and a first inductive interface; and

a second integrated circuit die having a second circuit and a second inductive interface;

a substrate coupled to support the first integrated circuit die and the second integrated circuit die, the substrate including a magnetic communication path aligned with the first inductive interface and the second inductive interface, to magnetically communicate signals between the first circuit and the second circuit;

wherein the magnetic communication path is aligned to magnetically communicate signals bidirectionally between the first circuit and the second circuit.

10. The integrated circuit of claim 9 wherein the first integrated circuit die is bonded to the substrate via a ferromagnetic glue.

11. The integrated circuit of claim 10 wherein the second integrated circuit die is bonded to the substrate via a ferromagnetic glue.

12. The integrated circuit of claim 9 wherein the first inductive interface includes a first coil and the second inductive interface includes a second coil.

13. The integrated circuit of claim 12 wherein the magnetic communication path includes a third coil aligned with the first coil and a fourth coil, coupled to the third coil and aligned with the second coil.

14. The integrated circuit of claim 13 wherein the third coil is planarly aligned with the first coil and the fourth coil is planarly aligned with the second coil.

15. The integrated circuit of claim 13 wherein the third coil is axially aligned with the first coil and the fourth coil is axially aligned with the second coil.

16. The integrated circuit of claim 9 wherein the magnetic communication path includes a ferromagnetic material.

17. The integrated circuit of claim 9 wherein the first integrated circuit die is stacked above the substrate and the second integrated circuit die is stacked below the substrate in a flip-chip configuration.