Wiring substrate having variously sized ball pads, semiconductor package having the wiring substrate, and stack package using the semiconductor package

• US 7,795,743 B2
• Filed: 10/05/2006
• Issued: 09/14/2010
• Est. Priority Date: 01/04/2006
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Kim, Tae-Hun, Kwon, Heung-Kyu, Byun, Hak-Kyoon, Park, Sung-Yong
• Primary Examiner(s): Williams; Alexander O
• Application Number:
  US11/539,133
• Publication Number:
  US 20070152350A1
• Time in Patent Office: 1,440 Days
• Field of Search: 257/786, 257/E23.02, 257/E23.069, 257/E23.07, 257/E23.194, 257/E25.013, 257/E25.023, 257/778, 257/737, 257/738, 257/772, 257/775, 257/776, 257/773, 257/780, 257/779, 257/668
• US Class Current: 257/786
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/4554 Coating
• CPC Class Codes: H01L 2224/48095 Kinked
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48228 the bond pad being disposed in a recess of the surface of the item
• CPC Class Codes: H01L 2224/48471 the other connecting portion not on the bonding area being a ball bond, i.e. wedge-to-ball, reverse stitch
• CPC Class Codes: H01L 2224/48479 on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2225/1023 the support being an insulating substrate
• CPC Class Codes: H01L 2225/1058 Bump or bump-like electrical connections, e.g. balls, pillars, posts
• CPC Class Codes: H01L 23/3128 the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/49816 Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/49838 Geometry or layout
• CPC Class Codes: H01L 23/562 Protection against mechanical damage H01L23/02, H01L23/28 take precedence
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/73 Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 25/105 : the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/15331 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/207 : Diameter ranges
• CPC Class Codes: H01L 2924/3511 : Warping
• CPC Class Codes: H05K 2201/09781 : Dummy conductors, i.e. not used for normal transport of current; Dummy electrodes of components
• CPC Class Codes: H05K 3/3436 : having an array of bottom contacts, e.g. pad grid array or ball grid array components
• CPC Class Codes: Y02P 70/50 : Manufacturing or production processes characterised by the final manufactured product

Abstract

A wiring substrate having variously sized ball pads, a semiconductor package including the wiring substrate, and a stack package using the semiconductor package, to improve board level reliability (BLR) of a semiconductor package or stack package mounted on a mother board are shown. Outer ball pads are formed to have relatively greater surface areas at the corners of the semiconductor package as compared to those at other areas and are formed to have the greatest surface area within a designable range. Additionally, occurrence of cracks may be inhibited at junctions of other solder balls by forming dummy solder pads at the outermost corners among the outer ball pads formed proximate to the corners of the wiring substrate. Stress arising during a board level reliability test is absorbed without product failure at junctions between the dummy solder pads and dummy solder balls.

Claims

1. A wiring substrate comprising:

a substrate body having an upper surface and lower surface, wherein an outer periphery of the lower surface includes outer corner regions and side regions extending between the outer corner regions;

a resin encapsulating area disposed on the upper surface of the substrate body and adapted to receive a semiconductor chip;

conductive wiring layers having bonding pads formed inside the resin encapsulating area and electrically connectable to a semiconductor chip when disposed within the resin encapsulating area;

upper ball pads formed on the upper surface of the substrate body; and

lower ball pads formed on the lower surface of the substrate body, wherein at least one of the wiring layers is electrically connected to at least one of the upper and lower ball pads,

wherein the lower ball pads include inner ball pads dispersed on a first area on the lower surface of the substrate opposite to the resin encapsulating area on the upper surface of the substrate, and outer ball pads dispersed on a second area on the lower surface of the substrate, wherein the second area surrounds the first area such that the outer ball pads are located in the outer periphery of the lower surface of the substrate,

wherein each of the outer ball pads has a greater surface area than each of the inner ball pads,

wherein the outer ball pads include first outer ball pads dispersed in each of the side regions of the outer periphery of the lower surface of the substrate, and second outer ball pads dispersed in each of the corner regions of the outer periphery of the lower surface of the substrate, and

wherein each of the second outer ball pads has a greater surface area than each of the first outer ball pads.

2. The wiring substrate of claim 1, wherein each of the second outer ball pads has the greatest surface area among the lower ball pads.

3. The wiring substrate of claim 2, wherein the outer ball pads are dispersed in a plurality of concentric rows surrounding the first area of the lower surface of the substrate.

4. The wiring substrate of claim 2, wherein an outer periphery of the first area on the lower surface of the substrate includes corner regions and side regions extending between the corner regions, and

wherein the inner ball pads comprise first inner ball pads dispersed in the side regions of the outer periphery of the first area on the lower surface of the substrate, and second inner ball pads dispersed in the corner regions of the outer periphery of the first area on the lower surface of the substrate, and

wherein a surface area of each of the first inner balls pads is greater than a surface area of each of the second inner ball pads.

5. The wiring substrate of claim 4, wherein the first inner ball pads are formed in a plurality of concentric rows on the outer periphery of the first area of the lower surface of the substrate.

6. The wiring substrate of claim 4, wherein the inner ball pads further include third inner ball pads located in a central region of the first area, each of the third inner ball pads having a smaller surface area than each of the first and second inner ball pads.

7. The wiring substrate of claim 4, wherein the area containing the second outer ball pads is greater than the area containing the corner first inner ball pads.

8. The wiring substrate of claim 1, wherein the wiring substrate further comprises insulating protection layers covering both surfaces of the substrate body including the conductive wiring layers except for the bonding pads, upper ball pads and lower ball pads.

9. The wiring substrate of claim 1, wherein the second outer ball pads include dummy ball pads formed proximate to outermost corners of the lower surface.

10. The wiring substrate of claim 1, wherein the upper ball pads include dummy ball pads formed proximate to outermost corners of the upper surface.

11. A semiconductor package comprising:

a wiring substrate comprising a substrate body having an upper surface and lower surface, wherein an outer periphery of the lower surface includes outer corner regions and side regions extending between the outer corner regions, and a resin encapsulating area disposed on the upper surface of the substrate body and adapted to receive a semiconductor chip;

a semiconductor chip mounted on the resin encapsulating area of the wiring substrate; and

a resin encapsulating section sealing the resin encapsulating area including the semiconductor chip;

wherein the wiring substrate further comprises conductive wiring layers having bonding pads formed inside the resin encapsulating area and electrically connected to the semiconductor chip, upper ball pads disperse on the upper surface of the substrate body, lower ball pads dispersed on the lower surface of the substrate body, and solder balls formed on lower ball pads, wherein at least one of the wiring layers is electrically connected to at least one of the upper and lower ball pads,

wherein the lower ball pads include inner ball pads dispersed on a first area on the lower surface of the substrate opposite to the resin encapsulating area on the upper surface of the substrate, and outer ball pads dispersed on a second area on the lower surface of the substrate, wherein the second area surrounds the first area such that the outer ball pads are located in the outer periphery of the lower surface of the substrate,

wherein each of the outer ball pads has a greater surface area than each of the inner ball pads,

wherein the outer ball pads include first outer ball pads dispersed in each of the side regions of the outer periphery of the lower surface of the substrate, and second outer ball pads dispersed in each of the corner regions of the outer periphery of the lower surface of the substrate, and

wherein each of the second outer ball pads has a greater surface area than each of the first outer ball pads.

12. The semiconductor package of claim 11, wherein the second outer ball pads include dummy ball pads formed proximate outermost corners of the lower surface of the wiring substrate.

13. The semiconductor package of claim 12, wherein the solder balls include dummy solder balls connected to the dummy ball pads.

14. The semiconductor package of claim 11, wherein the upper ball pads include dummy ball pads formed proximate outermost corners of the upper surface of the wiring substrate.

15. The semiconductor package of claim 11, further comprising an upper semiconductor package stacked on the upper ball pads and coupled thereto by solder bonding.

16. The semiconductor package of claim 15, wherein the upper package is a ball grid array type semiconductor package having solder balls on a lower surface thereof corresponding to the upper ball pads.

17. The semiconductor package of claim 16, wherein the second outer ball pads include dummy ball pads formed proximate outermost corners of the lower surface of the wiring substrate.

18. The semiconductor package of claim 17, wherein the solder balls include dummy solder balls connected to the dummy ball pads.

19. The stack package of claim 15, wherein the upper ball pads include dummy ball pads formed proximate to the outermost corners of the upper surface of the wiring substrate.

20. The stack package of claim 19, wherein solder balls of the upper package include dummy solder balls connected to the dummy ball pads.

21. A wiring substrate comprising:

a substrate body having an upper surface and lower surface, wherein an outer periphery of each of lower surface includes outer corner regions and side regions extending between the outer corner regions;

a resin encapsulating area disposed on a central region of the upper surface of the substrate body; and

conductive wiring layers including upper ball pads formed outside the resin encapsulating area, and

lower ball pads formed on the lower surface of the substrate body and dispersed in the outer corner regions and the side regions of the outer periphery of the lower surface of the substrate body,

wherein each of the lower ball pads located in the corner regions of the outer periphery of the lower surface of the substrate has a larger surface area than each of the lower ball pads located in the side regions of the outer periphery of the lower surface of the substrate.

22. The wiring substrate of claim 21, wherein the lower ball pads further comprise inner ball pads dispersed in an area opposite to the resin encapsulating area and each having a surface area which is less than that of the lower ball pads dispersed in the outer periphery of the lower surface of the substrate body.

23. A semiconductor package comprising:

a wiring substrate comprising a substrate body having an upper surface and lower surface, wherein an outer periphery of the lower surface includes outer corner regions and side regions extending between the outer corner regions, and a resin encapsulating area disposed on the upper surface of the substrate body and adapted to receive a semiconductor chip;

a semiconductor chip mounted on the resin encapsulating area of the wiring substrate; and

a resin encapsulating section sealing the resin encapsulating area including the semiconductor chip;

wherein the wiring substrate further comprises conductive wiring layers including upper ball pads formed outside the resin encapsulating area, and lower ball pads formed on the lower surface of the substrate body and dispersed in the outer corner regions and the side regions of the outer periphery of the lower surface of the substrate body,

wherein each of the lower ball pads located in the corner regions of the outer periphery of the lower surface of the substrate has a larger surface area than each of the lower ball pads located in the side regions of the outer periphery of the lower surface of the substrate, and

wherein solder balls are formed on the lower ball pads of the wiring substrate.

24. The semiconductor package of claim 23, wherein the lower ball pads further comprise inner ball pads dispersed in an area opposite to the resin encapsulating area and each having a surface area which is less than that of the lower ball pads dispersed in the outer periphery of the lower surface of the substrate body.

25. The semiconductor package of claim 24, further comprising an upper package stacked on upper ball pads and coupled thereto by solder bonding.

26. The semiconductor package of claim 25, wherein the upper package is a ball grid array type semiconductor package formed with solder balls on a lower surface thereof corresponding to the upper ball pads.