Semi-digital delay locked loop circuit and method

• US 7,795,937 B2
• Filed: 03/12/2009
• Issued: 09/14/2010
• Est. Priority Date: 03/26/2008
• Status: Active Grant

• Current Assignee: Xueshan Technologies Inc. (Wi-LAN Inc.)
• Original Assignee: MStar Semiconductor Incorporated (MediaTek, Inc.)
• Inventors: Yeh, Ellen Chen, Lu, Wen cai, Smith, Sterling
• Primary Examiner(s): Donovan; Lincoln
• Assistant Examiner(s): Houston; Adam D
• Application Number:
  US12/402,815
• Publication Number:
  US 20090243679A1
• Time in Patent Office: 551 Days
• Field of Search: 327/149, 327/158
• US Class Current: 327/158
• CPC Class Codes: H03L 7/07 using several loops, e.g. for redundant clock signal generation
• CPC Class Codes: H03L 7/0814 the phase shifting device being digitally controlled
• CPC Class Codes: H03L 7/0996 Selecting a signal among the plurality of phase-shifted signals produced by the ring oscillator
• CPC Class Codes: H04N 5/126 whereby the synchronisation signal indirectly commands a frequency generator

Abstract

A scalable DLL (delay locked loop) circuit that has a calibration mechanism to auto tune locking precision. The delay locked loop circuit includes a multi-phase phase locked loop circuit for generating a plurality of phase signals according to a system clock, wherein one of the phase signals is a pixel clock; a phase detector for detecting an integral phase error and a fractional phase error between a reference signal and a feedback signal according to the pixel clock; a phase selector for selecting one of the phase signals according to the fractional phase error; and a delay circuit for shifting the phase of the reference signal according to the integral phase error and the selected phase signal to generate an output signal.

Claims

1. A delay locked loop circuit, comprising:

a multi-phase phase locked loop circuit for generating a plurality of phase signals according to a system clock, wherein one of the phase signals is a pixel clock;

a phase detector for detecting an integral phase error and a fractional phase error between a reference signal and a feedback signal according to the pixel clock;

a phase selector for selecting one of the phase signals to be a selected phase signal according to the fractional phase error; and

a delay circuit for shifting the phase of the reference signal according to the integral phase error and the selected phase signal to generate an output signal, wherein the feedback signal is associated with the output signal.

2. The delay locked loop circuit as claimed in claim 1, wherein the phase detector comprises:

an integral clock counter for counting the pulse of the pixel clock to generate a count;

a phase quantizer for generating an integral reference phase, a fractional reference phase, an integral feedback phase and a fractional feedback phase according to the reference signal, the feedback signal, the count and the phase signals; and

a phase subtractor for calculating the difference between the integral feedback phase and the integral feedback phase to generate the integral phase error, and calculating the difference between the fractional feedback phase and the fractional feedback phase to generate the fractional phase error.

3. The delay locked loop circuit as claimed in claim 2, wherein the integral clock counter is reset at each rising edge of the reference signal.

4. The delay locked loop circuit as claimed in claim 2, wherein the phase quantizer generates the integral reference phase and the integral feedback phase by reading the count at the rising edge of the reference signal and the feedback signal respectively.

5. The delay locked loop circuit as claimed in claim 2, wherein the phase quantizer generates the fractional reference phase and the fractional feedback phase by comparing the reference signal and the feedback phase with the phase signals respectively.

6. The delay locked loop circuit as claimed in claim 2, wherein the phase quantizer comprises a time-to-digital converter for generating the fractional reference phase and the fractional feedback phase according to the reference signal, the feedback phase and the phase signals.

7. The delay locked loop circuit as claimed in claim 1, further comprising:

a loop filter unit for filtering the integral phase error and the fractional phase error outputted by the phase detector to generate an integral output phase to the delay circuit and the fractional output phase to the phase selector.

8. The delay locked loop circuit as claimed in claim 7, further comprising:

a phase offset unit for providing an instantaneous phase offset of the pixel clock;

a first adder for adding the instantaneous phase offset into the integral phase error and the fractional phase error before the loop filter; and

a second adder for adding the instantaneous phase offset into the integral output phase and the fractional output phase after the loop filter.

9. A method for adjusting the phase between a reference signal and a feedback signal, the method comprising steps of:

generating a plurality of phase signals according to a system clock, wherein one of the phase signals is a pixel clock;

detecting an integral phase error and a fractional phase error between the reference signal and the feedback signal according to the pixel clock;

selecting a selected phase signal from the phase signals according to the fractional phase error; and

shifting the phase of the reference signal according to the integral phase error and the selected phase signal to generate an output signal, wherein the feedback signal is associated with the output signal.

10. The method as claimed in claim 9, wherein the step of detecting an integral phase error and a fractional phase error comprises steps of:

counting a pulse of the pixel clock to generate a count;

generating an integral reference phase, a fractional reference phase, an integral feedback phase and a fractional feedback phase according to the reference signal, the feedback signal, the count and the phase signals; and

calculating the difference between the integral feedback phase and the integral feedback phase to generate the integral phase error and calculating the difference between the fractional feedback phase and the fractional feedback phase to generate the fractional phase error.

11. The method as claimed in claim 9, wherein the reference signal is obtained by processing a horizontal synchronization signal.

12. The method as claimed in claim 10, wherein the count is reset to zero at each rising edge of the reference signal.

13. The method as claimed in claim 10, wherein the integral reference phase and the integral feedback phase are generated by reading the count at the rising edge of the reference signal and the feedback signal respectively.

14. The method as claimed in claim 10, wherein the fractional reference phase and the fractional feedback phase are generated by comparing the reference signal and the feedback phase with the phase signals respectively.

15. The method as claimed in claim 9, further comprising:

filtering the integral phase error and the fractional phase error to generate an integral output phase and a fractional output phase.

16. The method as claimed in claim 15, further comprising:

adding the instantaneous phase offset into the integral phase error and the fractional phase error before the filtering step; and

adding the instantaneous phase offset into the integral output phase and the fractional output phase after the filtering step.