Power ranging transmit RF power amplifier

• US 7,795,968 B1
• Filed: 01/12/2009
• Issued: 09/14/2010
• Est. Priority Date: 01/12/2008
• Status: Active Grant

• Current Assignee: pSemi Corporation (Murata Manufacturing Co Limited)
• Original Assignee: Peregrine Semiconductor Corporation (Murata Manufacturing Co Limited)
• Inventors: Li, Yang, Bacon, Peter, Broughton, Robert, Bonkowski, James
• Primary Examiner(s): CHOE, HENRY
• Application Number:
  US12/319,898
• Time in Patent Office: 610 Days
• Field of Search: 330/129, 330/124.D, 330/51, 330/302
• US Class Current: 330/129
• CPC Class Codes: H03F 1/223 with MOSFET's
• CPC Class Codes: H03F 1/56 Modifications of input or output impedances, not otherwise provided for
• CPC Class Codes: H03F 2203/7233 the gated amplifier, switched on or off by putting into parallel or not, by choosing between amplifiers by one or more switch(es), being impedance adapted by switching an adapted passive network
• CPC Class Codes: H03F 3/195 in integrated circuits
• CPC Class Codes: H03F 3/72 Gated amplifiers, i.e. amplifiers which are rendered operative or inoperative by means of a control signal

Abstract

An RF PA operable in two or more selectable power ranges is disclosed. Switches configure the circuit for each range such that an amplifier device corresponding to the range provides final amplification, and all lower power amplifier devices also amplify the signal. An exemplary design includes a low power amplifier configurable for operation solo, or in parallel with a medium power amplifier, to deliver an appropriately matched signal either directly to the RF PA output, or first to the input of a high power amplifier for the highest power range. The signal in all ranges of the exemplary design is conditioned in part by the matching circuitry disposed between the high power amplifier and the RF PA output, which traverses no switches in high power range operation. The entire RF PA, including switches, control and matching circuitry, is fabricated on a single monolithic integrated circuit, an achievement may be facilitated by UTSI CMOS processing.

Claims

1. An RF (radio frequency) PA (power amplifier) for amplifying an RF signal between a source node IN and an output node OUT in a selectable plurality of output power ranges including a low power range and a high power range, the RF PA comprising:

a) a low power active amplifier device configured as a final amplification stage when the RF PA operates in the low power range, and configured as a first amplification stage when the RF PA operates in the high power range; and

b) a high power active amplifier circuit configured to conduct significant operating current and to amplify a signal previously amplified by the low power active amplifier device when the RF PA operates in the high power range, and configured to conduct less than 5% of the significant operating current when the RF PA operates in the low power range.

2. The RF PA of claim 1, wherein the high power active amplifier circuit is configured to conduct less than 0.5% of the significant operating current when the RF PA operates in the low power range.

3. The RF PA of claim 1, further comprising a medium power active amplifier circuit configured to conduct a suitable operating current when the RF PA operates in a medium power range or in the high power range, but to conduct less than 5% of the suitable operating current when the RF PA operates in a low power range.

4. The RF PA of claim 3 wherein an output of the medium power active amplifier device is coupled directly to the output of the low power active amplifier device, and both devices are configured to amplify the signal when the RF PA operates in the medium power range.

5. The RF PA of claim 1, further comprising matching circuitry configurable by configuration switches to establish an approximately same selected impedance at the output node OUT regardless of a power range in which the RF PA operates, including high power matching circuitry disposed to match impedance between an output of the high power active amplifier circuit and the output node OUT that includes no configuration switch intended to conduct when the RF PA operates in the high power range.

6. The RF PA of claim 5, wherein circuitry configured to match an output of the low power amplifier device to the RF PA output OUT includes the high power matching circuitry when the RF PA operates in any power range other than the high power range.

7. The RF PA of claim 4, wherein all components of the RF PA are fabricated by a same integrated circuit process.

8. The RF PA of claim 7, wherein the integrated circuit process is CMOS silicon on insulator.

9. The RF PA of claim 6, wherein all FETs forming part of any configuration switch or any active amplifier device have an insulated gate.

10. The RF PA of claim 9, further fabricated on a single monolithic integrated circuit.

11. A method of amplifying an RF (radio frequency) signal between an input node IN and an output node OUT of an RF PA (power amplifier) in a selectable plurality of power ranges including a low power range and a high power range, comprising:

a) selecting a low power range, and while operating in that range

i) coupling a signal presented on the input node IN to an input of a low power active amplifier device,

ii) amplifying the signal between the input and an output of the low power active amplifier device, and

iii) coupling the amplified signal from the output of the low power active amplifier device to the output node OUT without further amplification,

b) selecting a high power range, and while operating in that range

i) coupling a signal presented on the input node IN to an input of the low power active amplifier device,

ii) amplifying the signal between the input and the output of the low power active amplifier device,

iii) coupling the amplified signal from the output of the low power active amplifier device to an input of a high power active amplifier device,

iv) amplifying the signal between the input and an output of the high power active amplifier device, and

v) coupling the signal amplified by both the low power active amplifier device and the high power active amplifier device from the output of the high power active amplifier device to the output node OUT.

12. The method of claim 11, further comprising conducting at least 200 times more current in the high power active amplifier device when operating in the high power range than when operating in the low power range.

13. The method of claim 11, further comprising c) selecting a medium power range, and while operating in that range

i) coupling a signal presented on the input node IN to an input of a medium power active amplifier device,

ii) amplifying the signal between the input and an output of the medium power active amplifier device, and

iii) coupling the amplified signal from the output of the medium power active amplifier device to the output node OUT without further amplification.

14. The method of claim 13, further comprising amplifying the signal by means of the low power amplifier device between the input node IN and the output of the medium power amplifier when operating in the medium power range.

15. The method of claim 11, further comprising coupling a high power signal at the output of the high power amplifier device to the output node OUT when operating in the high power range via high power matching circuit elements without conducting the high power signal through a configuration switch, and switching matching circuit elements via configuration switches in all selectable ranges to establish an impedance of the signal at the output node OUT to have an approximately same nominal value.

16. The method of claim 15, further comprising coupling the amplified signal to the output node OUT via the high power matching circuit elements when operating in any power range other than the high power range.

17. The method of claim 16, further comprising amplifying, switching and conditioning the signal from the input node IN to the output node OUT exclusively via elements fabricated by a same integrated circuit process.

18. The method of claim 17, wherein the same integrated circuit process is a CMOS silicon on insulator process.

19. The method of claim 14, further comprising amplifying and switching the signal from the input node IN to the output node OUT via FETs without using any non-insulated gate FETs.

20. The method of claim 19, further comprising amplifying, switching and conditioning the signal from the input node IN to the output node OUT exclusively via elements fabricated on a same monolithic integrated circuit.