Abnormal circuit operation detection system

• US 7,796,050 B2
• Filed: 08/22/2005
• Issued: 09/14/2010
• Est. Priority Date: 03/29/2005
• Status: Expired due to Fees

• Current Assignee: Fujitsu Limited
• Original Assignee: Fujitsu Limited
• Inventors: Iwaki, Hiroyuki, Ikeda, Yoshihisa, Hashizume, Masato, Yasui, Takanori, Hashimoto, Chikashi
• Primary Examiner(s): Goins; Davetta W
• Assistant Examiner(s): Labbees; Edny
• Application Number:
  US11/207,831
• Publication Number:
  US 20060242463A1
• Time in Patent Office: 1,849 Days
• Field of Search: 340/657, 340/658, 340/659, 340/661, 340/662, 340/663, 340/664, 340/679, 340/680, 361/6, 361/90, 361/91.1, 361/5
• US Class Current: 340/679
• CPC Class Codes: G01R 31/3004 Current or voltage test

Abstract

An abnormality in operation is detected by meticulously monitoring the operation of a monitored device that comprises a state machine. The state number, indicating the state the monitored device is currently in, is output from the device. The upper and lower limit values of current consumption is set for each state number. A monitoring circuit, using the upper and lower limit values for the present state number, judges the value of current consumption detected by a current detection circuit and detects whether there is abnormality in operation.

Claims

1. An abnormal operation detection system comprising:

a monitored integrated circuit device having a configuration of a state machine in which a plurality of states and conditions for state transitions are defined, said monitored integrated circuit device having a function to output a state number indicating a state of said state machine;

a power consumption detection circuit detecting power consumption of said monitored integrated circuit device; and

a monitoring circuit determining the presence or absence of abnormality in said detected power consumption by using an abnormality evaluation value corresponding to the state number output from said monitored integrated circuit device.

2. An abnormal operation detection system according to claim 1, wherein said monitoring circuit further determines the presence or absence of an abnormality in said power consumption by using accumulated power consumption values, which represent the value of the power consumption accumulated for a predetermined length of time irrespective of said state number, and an abnormality evaluation value predetermined for said accumulated power consumption values.

3. An abnormal operation detection system according to claim 1, further comprising a control circuit for sequentially supplying a plurality of test patterns to said monitored integrated circuit device, and wherein

said monitoring circuit further determines the presence or absence of an abnormality in said power consumption by using an abnormality evaluation value corresponding to the test pattern that said control circuit supplies to said monitored integrated circuit device.

4. The abnormal operation detection system according to claim 1, wherein said monitoring circuit has an external storage device storing an abnormality evaluation value for each state of said monitored integrated circuit device.

5. The abnormal operation detection system according to claim 1, further comprising a temperature sensor detecting a temperature on said monitored integrated circuit device, and wherein

said monitoring circuit further determines the presence or absence of an abnormality using an abnormality evaluation value corresponding to the temperature detected by said temperature sensor.

6. The abnormal operation detection system according to claim 1, wherein:

plural states, respective, expected ranges of values of power consumption are defined, in advance, and

the monitoring circuit monitors the current power consumption and compares each monitored value of power consumption with the expected range of power consumption for the current state number and, when the monitored power consumption is outside of the expected range for the current state number, resets the monitoring device to restore it to a normal condition.

8. The abnormal operation detection system according to claim 1, wherein the monitored integrated circuit device is selected from the group consisting of a Field Programmable Gate Array and an Application Specific Integrated Circuit.

7. A system, comprising:

a monitored integrated circuit device having a configuration of a state machine having internal states and conditions for state transitions of the monitored integrated circuit device and outputting numerical values indicating internal states of said monitored integrated circuit device;

a power consumption detection circuit detecting power consumption of said monitored integrated circuit device; and

a monitoring circuit determining abnormality in the power consumption by comparing abnormality values to the numerical values output from said monitored integrated circuit device.