Multi-GPU graphics processing subsystem for installation in a PC-based computing system having a central processing unit (CPU) and a PC bus

• US 7,796,129 B2
• Filed: 10/23/2007
• Issued: 09/14/2010
• Est. Priority Date: 11/19/2003
• Status: Active Grant

• Current Assignee: Google LLC (Alphabet Inc.)
• Original Assignee: Lucid Information Technology, Ltd.
• Inventors: Bar-or, Gigy, Shaham, Amir, Bakalash, Reuven, Fogel, Efi, Remez, Offir
• Primary Examiner(s): Nguyen, Hau H
• Application Number:
  US11/977,161
• Publication Number:
  US 20080165197A1
• Time in Patent Office: 1,057 Days
• Field of Search: 345502-506, 345/519, 345/520, 345/419, 345/522
• US Class Current: 345/419
• CPC Class Codes: G06F 3/14 Digital output to display device ; Cooperation and interconnection of the display device with other functional units
• CPC Class Codes: G06F 3/1438 using more than one graphics controller
• CPC Class Codes: G06F 9/505 considering the load
• CPC Class Codes: G06T 1/20 Processor architectures; Processor configuration, e.g. pipelining
• CPC Class Codes: G06T 15/005 General purpose rendering architectures
• CPC Class Codes: G06T 2200/28 involving image processing hardware
• CPC Class Codes: G09G 5/363 Graphics controllers

Abstract

A multi-GPU graphics processing subsystem for installation in a PC-based computing system having a CPU and a CPU interface module including a PC bus. The graphics processing subsystem interfaced with the CPU interface module by way of the PC bus, and a display surface for displaying said images by graphically displaying frames of pixel data produced by the graphics processing subsystem. The graphics processing subsystem includes a plurality of GPUs arranged in a parallel architecture and operating according to a parallelization mode of operation so that each GPU supports a graphics pipeline and is allowed to process data in a parallel manner. A hardware hub, interfaces with the CPU interface module and the GPUs, by way of the PC bus, and has a hub router for (i) distributing the stream of geometrical data and graphic commands among the GPUs, and (ii) transferring pixel data output from one or more of GPUs during the composition of frames of pixel data corresponding to final images for display on the display surface. The CPU interface module provides an interface between one or more software hub drivers and the hardware hub.

Claims

1. A multi-GPU graphics processing subsystem integrated in a PC-based computing system including (i) system memory for storing software graphics applications, software drivers and graphics libraries, (ii) an operating system (OS), stored in said system memory, (iii) one or more graphics applications, stored in said system memory, for generating a stream of geometrical data and graphics commands supporting the representation of one or more 3D objects in a scene having 3D geometrical characteristics and the viewing of images of said one or more 3D objects in said scene during an interactive process carried out between said PC-based computing system and a user of said PC-based computing system, (iv) one or more graphic libraries, stored in said system memory, for storing data used to implement said stream of geometrical data and graphics commands, (v) a central processing unit (CPU), for executing said OS, said graphics applications, said drivers and said graphics libraries, (vi) a CPU interface module and a PC bus, and (vii) a display surface for displaying said images by graphically displaying frames of pixel data produced by said multi-GPU graphics processing subsystem;

wherein said multi-GPU graphics processing subsystem is interfaced with said CPU interface module by way of said PC bus and comprises;

a plurality of graphic processing units (GPUs) arranged in a parallel architecture and operating according to a parallelization mode of operation so that said GPUs support multiple graphics pipelines and process data in a parallel manner;

one or more GPU drivers, stored in said system memory, for allowing said GPUs to interact with said graphic libraries;

one or more software hub drivers, stored in said system memory;

a hardware hub, interfacing with said CPU interface module and said GPUs, by way of said PC bus, and having a hub router for (i) distributing the stream of geometrical data and graphic commands among said GPUs, and (ii) transferring pixel data output from one or more of said GPUs during the composition of frames of pixel data corresponding to final images for display on said display surface;

wherein said CPU interface module provides an interface between said one or more software hub drivers and said hardware hub;

wherein said one or more software hub drivers perform the following functions;

(i) controlling the operation of said hardware hub,

(ii) interacting with said OS and said graphic libraries, and

(iii) forwarding said stream of geometrical data and graphic commands, or a portion thereof, to each said GPU over said PC bus; and

wherein, for each image of said 3D object to be generated and displayed on said display surface, the following operations are performed;

(i) said hardware hub uses said hub router and said PC bus to distribute said stream of geometrical data and graphic commands, or a portion thereof, to said GPUs,

(ii) one or more of said GPUs process said stream of geometrical data and graphic commands, or a portion thereof, during the generation of each said frame, while operating in said parallelization mode, so as to generate pixel data corresponding to at least a portion of said image, and

(iii) said hardware hub uses said router and said PC bus to transfer said pixel data output from one or more of said GPUs and compose a frame of pixel data, representative of the image of said 3D object, for display on said display surface.

2. The multi-GPU graphics processing subsystem of claim 1, wherein said CPU interface module comprises an I/O module.

3. The multi-GPU graphics processing subsystem of claim 2, wherein said I/O module comprises an I/O chip or chipset.

4. The multi-GPU graphics processing subsystem of claim 1, wherein each said GPU has a frame buffer (FB) for storing a fragment of pixel data.

5. The multi-GPU graphics processing subsystem of claim 1, wherein said geometrical data comprises a set of scene polygons or vertices.

6. The multi-GPU graphics processing subsystem of claim 1, wherein said graphics commands includes commands selected from the group consisting of display lists and display vertex arrays.

7. The multi-GPU graphics processing subsystem of claim 1, wherein said hardware hub further comprises a control unit for accepting commands from said one or more software hub drivers, over said PC bus, and controlling components within said hardware hub, including said hub router.

8. The multi-GPU graphics processing subsystem of claim 1, wherein said hub router routes said stream of geometrical data and graphic commands from said graphics application to one or more of said GPUs, and wherein said hub router routes pixel data results from said GPUs during the composition of said frame of pixel data.

9. The multi-GPU graphics processing subsystem of claim 1, wherein said hardware hub further comprises a memory unit for storing intermediate processing results from one or more of said multiple GPUs and data required for composition and transferring frames of pixel data for display.

10. The multi-GPU graphics processing subsystem of claim 1, wherein said one or more software hub drivers control said GPUs while said hardware hub operates transparently to said one or more graphics applications so that said multiple GPUs appear as only a single GPU to said one or more graphics applications.

11. The multi-GPU graphics processing subsystem of claim 1, wherein said one or more software hub drivers coordinate the operation of said GPUs so as to generate a continuous sequence of frames of pixel data for displaying a sequence of images of said 3D object on said display surface.

12. The multi-GPU graphics processing subsystem of claim 1, wherein said hardware hub handles multiple bus paths between said CPU and said GPUs.

13. The multi-GPU graphics processing subsystem of claim 1, wherein said parallelization mode of operation is a time division mode of parallel operation, wherein each said GPU renders a different frame of pixel data for display on said display surface at a different moment of time.

14. The multi-GPU graphics processing subsystem of claim 1, wherein said parallelization mode of operation is an image division mode of parallel operation, wherein each GPU renders a subset of pixels used to compose each frame of pixel data to be displayed on said display surface.

15. The multi-GPU graphics processing subsystem of claim 1, wherein said parallelization mode of operation is an object division mode of parallel operation, wherein each said 3D object which is to be displayed as an image consisting of a frame of pixels, is decomposed into said stream of geometrical data and graphic commands which are distributed to said GPUs for rendering the frames of pixel data compositing the images to be displayed on said display surface.

16. The multi-GPU graphics processing subsystem of claim 1, wherein each said 3D object is decomposable into a plurality of polygons, and wherein said geometrical data comprises the vertices of said polygons.

17. The multi-GPU graphics processing subsystem of claim 1, wherein each pixel associated with a frame of pixel data includes attributes selected from the group consisting of color, alpha, position, depth, and stencil.