Universal three phase controllers for power converters

• US 7,796,411 B2
• Filed: 12/30/2008
• Issued: 09/14/2010
• Est. Priority Date: 10/30/2003
• Status: Active Grant

• Current Assignee: Regents of the University of California (University of California)
• Original Assignee: Regents of the University of California (University of California)
• Inventors: Jin, Taotao, Smedley, Keyue
• Primary Examiner(s): Berhane; Adolf
• Assistant Examiner(s): PHAM, EMILY P
• Application Number:
  US12/346,465
• Publication Number:
  US 20090303764A1
• Time in Patent Office: 623 Days
• Field of Search: 363/39, 363 44- 48, 363/82, 363/84, 363 87- 92, 363125-128, 323/910, 323/212, 323/237
• US Class Current: 363/89
• CPC Class Codes: H02J 3/1842 wherein at least one reactive element is actively controlled by a bridge converter, e.g. active filters
• CPC Class Codes: H02M 1/0012 Control circuits using digital or numerical techniques in DC/DC converters H02M3/157, H02M3/33515; in DC-AC converters H02M7/53873
• CPC Class Codes: H02M 1/4233 using a bridge converter comprising active switches
• CPC Class Codes: H02M 7/2173 in a biphase or polyphase circuit arrangement H02M7/2176 takes precedence; voltage multipliers H02M7/25
• CPC Class Codes: H02M 7/219 in a bridge configuration
• CPC Class Codes: H02M 7/487 Neutral point clamped inverters
• CPC Class Codes: H02M 7/53875 with analogue control of three-phase output
• CPC Class Codes: Y02B 70/10 Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
• CPC Class Codes: Y02E 40/20 Active power filtering [APF]
• CPC Class Codes: Y02P 80/10 Efficient use of energy, e.g. using compressed air or pressurized fluid as energy carrier
• CPC Class Codes: Y10S 323/91 Two of three phases regulated

Abstract

The systems and methods described herein provide for a universal controller capable of controlling multiple types of three phase, two and three level power converters. The universal controller is capable of controlling the power converter in any quadrant of the PQ domain. The universal controller can include a region selection unit, an input selection unit, a reference signal source unit and a control core. The control core can be implemented using one-cycle control, average current mode control, current mode control or sliding mode control and the like. The controller can be configured to control different types of power converters by adjusting the reference signal source. Also provided are multiple modulation methods for controlling the power converter.

Claims

1. A three-phase universal controller, comprising;

a reference signal source unit integrated with a one-cycle control (OCC) controller and configured to inject reference signal into the OCC controller, the OCC controller comprising;

a control core configured to generate a plurality of pulse width modulated (PWM) duty-ratio drive signals;

a voltage loop compensator coupled with the control core and configured to take a taking reference voltage Vref and DC voltage feedback signal proportional to an output DC voltage Vo of a three-phase power converter and provide an output Vm coupled to the control core;

a region selection unit configured to detect a first, second and third time-varying line voltage signals, each line voltage signal having a different phase, and configured to determine a region of operation based on zero crossings of all three time-varying voltage signals;

a signal selection unit coupled with the region selection unit and the control core and configured to select two or more line current signals flowing through the first, second and third time varying line voltage sources and the reference signal and based on the region of operation and provide the selected signals to the control core; and

a drive signal distribution unit coupled to the control core and the region selection unit, the drive signal distribution unit configured to distribute the PWM duty ratio drive signals from the control core to switches of a three-phase converter to realize non grid-tied inverters, static voltage-ampere-reactive (VAR) compensators (SVC), or power converters with the capability of any combination of a power factor corrected rectifier, a grid-tied inverter, a non-grid-tied inverter, a SVC, and an active power filter.

2. The controller of claim 1, wherein the signal selection unit is configured to combine the reference signal with the line current signals flowing through the time varying line voltage sources.

3. The controller of claim 1, wherein the reference signals are determinable as a function of an adjustable phase offset value, an adjustable gain value, and the input time varying line voltages to a power converter, wherein

$\left[\begin{array}{c}{i}_{\mathrm{aref}}\\ i_{\mathrm{bref}}\\ i_{\mathrm{cref}}\end{array}\right]=G_e·$

ⅇ

j ·

θ

⁡

[ v a v b v c ]

and wherein G_e is the gain value, θ

is the phase offset value, V_a, V_b and V_c are input time varying line voltages to the power converter and i_aref, i_bref and i_cref are the reference signals corresponding to V_a, V_b and V_c; and

, wherein the OCC having universal control ability utilizing the reference signals and utilizing different gain values and phase offset values.

4. The controller of claim 3, wherein the phase offset value and the gain value are predetermined to enable a three-phase two or three-level power converter to operate under zero DC or AC load condition.

5. The controller of claim 1, wherein the control core includes an analog, digital, and/or microcontroller circuitry configured to implement a control key equation to control a three-phase two-level power converter, wherein:

$V_m·<br><br>\left[\begin{array}{c}1-d_p\\ 1-d_n\end{array}\right]=\left[\begin{array}{cc}2& 1\\ 1& 2\end{array}\right]·<br><br>\left[\begin{array}{c}{R}_s·<br><br>i_p\\ R_s·<br><br>i_n\end{array}\right]-G_e·<br><br>{\mathrm{e<br><br>}}^{j·<br><br>\mathrm{\theta <br><br>}}·<br><br>\left[\begin{array}{cc}2& 1\\ 1& 2\end{array}\right]·<br><br>\left[\begin{array}{c}{v}_p\\ v_n\end{array}\right]$

wherein;

G_e is the gain value, θ

is the phase offset value,

V_m is the output signal of the voltage loop compensator,

d_p and d_n are the duty ratio drive signals from the control core,

i_p and i_n are the selected line current signals from the signal selection unit,

R_s is the sensing resistance for the line current signals,

v_p and v_n are the selected voltage signals from the signal selection unit, and

p and n are valued a and c, b and c, b and a, c and a, c and b, or a and b respectively depending on the region.

6. The controller of claim 1, wherein the control core includes an analog, digital, and/or microcontroller circuitry configured to implement a control key equation to control a three-phase three-level power converter, wherein:

$V_m·<br><br>\left[\begin{array}{c}1-d_p\\ 1-d_n\end{array}\right]=\left[\begin{array}{cc}2& -1\\ -1& 2\end{array}\right]·<br><br>\left[\begin{array}{c}{R}_s·<br><br>i_p\\ R_s·<br><br>i_n\end{array}\right]-G_e·<br><br>{\mathrm{e<br><br>}}^{j·<br><br>\mathrm{\theta <br><br>}}·<br><br>\left[\begin{array}{cc}2& -1\\ -1& 2\end{array}\right]·<br><br>\left[\begin{array}{c}{v}_p\\ v_n\end{array}\right]$

wherein;

G_e is the gain value, θ

is the phase offset value,

V_m is the output signal of the voltage loop compensator,

d_p and d_n are the duty ratio drive signals from the control core,

i_p and i_n are the selected line current signals from the signal selection unit,

R_s is the sensing resistance for the line current signals,

v_p and v_n are the selected voltage signals from the signal selection unit, and

p and n are valued a and c, b and c, b and a, c and a, c and b, or a and b respectively depending on the region.

7. The controller of claim 1, wherein the control core includes an analog, digital, and/or microcontroller circuitry configured to implement a control key equation to control a three-phase three-level power converter, wherein:

$V_m·<br><br>\left[\begin{array}{c}1-2·<br><br>d_p\\ 1-2·<br><br>d_n\end{array}\right]=\left[\begin{array}{cc}2& -1\\ -1& 2\end{array}\right]·<br><br>\left[\begin{array}{c}{R}_s·<br><br>i_p\\ R_s·<br><br>i_n\end{array}\right]-G_e·<br><br>{\mathrm{e<br><br>}}^{j·<br><br>\mathrm{\theta <br><br>}}·<br><br>\left[\begin{array}{cc}2& -1\\ -1& 2\end{array}\right]·<br><br>\left[\begin{array}{c}{v}_p\\ v_n\end{array}\right]$

wherein;

G_e is the gain value, θ

is the phase offset value,

V_m is the output signal of the voltage loop compensator,

d_p and d_n are the duty ratio drive signals from the control core,

i_p and i_n are the selected line current signals from the signal selection unit,

R_s is the sensing resistance for the line current signals,

v_p and v_n are the selected voltage signals from the signal selection unit, and

p and n are valued a and c, b and c, b and a, c and a, c and b, or a and b respectively depending on the region.

8. The controller of claim 1, wherein the control core includes an analog, digital, and/or microcontroller circuitry configured to implement a control key equation to control a three-phase three-level power converter, wherein:

$V_m·<br><br>\left[\begin{array}{c}1-d_p/2\\ 1-d_n\end{array}\right]=\frac{1}{2}·<br><br>\left[\begin{array}{cc}2& 1\\ 1& 2\end{array}\right]<br><br>\left[\begin{array}{c}{R}_s·<br><br>i_p\\ R_s·<br><br>i_n\end{array}\right]-\frac{G_e·<br><br>{\mathrm{e<br><br>}}^{j·<br><br>\mathrm{\theta <br><br>}}}{2}·<br><br>\left[\begin{array}{cc}2& 1\\ 1& 2\end{array}\right]·<br><br>\left[\begin{array}{c}{v}_p\\ v_n\end{array}\right]$

wherein;

G_e is the gain value, θ

is the phase offset value,

V_m is the output signal of the voltage loop compensator,

d_p and d_n are the duty ratio drive signals from the control core,

i_p and i_n are the selected line current signals from the signal selection unit,

R_s is the sensing resistance for the line current signals,

v_p and v_n are the selected voltage signals from the signal selection unit, and

p and n are valued a and c, b and c, b and a, c and a, c and b, or a and b respectively depending on the region.

9. The controller of claim 1, wherein the control core is a current mode control core, sliding mode control core, or average current mode control core to control the three-phase two or three level power converter realizing a power factor corrected rectifier, a grid-tied inverter, a non-grid-tied inverter, a SVC, an active power filter, or a converter with the capability of any combination of a power factor corrected rectifier, a grid-tied inverter, a non-grid-tied inverter, a SVC, an active power filter.

10. The controller of claim 1, wherein the line current signals are sensed physically at the line voltage sources or mathematically constituted from signals sensed any where in the power converter.