Semiconductor memory device and write method thereof

• US 7,796,439 B2
• Filed: 01/22/2008
• Issued: 09/14/2010
• Est. Priority Date: 01/23/2007
• Status: Expired due to Fees

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Sato, Atsuhiro, Arai, Fumitaka, Kamigaichi, Takeshi
• Primary Examiner(s): Nguyen; Tuan T
• Assistant Examiner(s): LE, TOAN K
• Application Number:
  US12/017,543
• Publication Number:
  US 20080181009A1
• Time in Patent Office: 966 Days
• Field of Search: 365/185.17, 365/185.18, 365/185.22, 365/185.24, 365/189.09, 365/189.05
• US Class Current: 365/185.22
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/3454 Arrangements for verifying correct programming or for detecting overprogrammed cells
• CPC Class Codes: G11C 16/3459 Circuits or methods to verify correct programming of nonvolatile memory cells
• CPC Class Codes: G11C 2211/5621 Multilevel programming verification
• CPC Class Codes: G11C 2211/5622 Concurrent multilevel programming of more than one cell
• CPC Class Codes: G11C 2211/5642 Multilevel memory with buffers, latches, registers at input or output

Abstract

A semiconductor memory device includes a memory cell array, bit lines, a source line, a sense amplifier, a data buffer, a voltage generating circuit, and a control circuit, the control circuit being configured such that the control circuit writes batchwise the write data, in the plurality of memory cells of the bit lines, the control circuit, after the batchwise write, causes the plurality of first latch circuits to hold the write data once again, and the control circuit executes verify read from the memory cells, and executes, in a case where read data of the plurality of sense amplifier circuits by the verify read disagree with the write data that are held once again in the plurality of first latch circuits, additional write to write batchwise the held write data in the plurality of memory cells once again.

Claims

1. A semiconductor memory device comprising:

a memory cell array having a plurality of memory cell strings arranged along a first direction respectively, each of the memory cell strings including a plurality of memory cells having current paths connected in series along a second direction which is perpendicular to the first direction, each of the memory cells having a charge accumulation layer and a control electrode, the control electrode extending in the first direction and connected to a memory cell located in an adjacent memory cell string;

a plurality of bit lines extending in the second direction, each of the bit lines electrically connected to one end of the current path of the associated memory cell string;

a source line extending in the first direction and electrically connected to the other end of the current paths of the memory cell strings;

a sense amplifier including a plurality of sense amplifier circuits, each of the sense amplifier circuit electrically connected to one of the bit lines, respectively;

a data buffer including a plurality of first latch circuits, each of the first latch circuits electrically connected to one of the bit lines;

an input terminal holding data from an external device; and

a control circuit executing a first verify write operation and a second verify write operation;

the first verify write operation including,

loading data from the input terminal to each of the first latch circuits,

writing each loaded data in the first latch circuits to one of the memory cells connected one of the bit lines, respectively,

reading the written data of the memory cells into the sense amplifier circuits,

verifying whether threshold voltages based on the written data are larger than a predetermined voltage, and

rewiring to a memory cell storing a written data having a threshold voltage which is smaller than the predetermined voltage; and

the second verify write operation including,

reloading the data from the input terminal to each of the first latch circuits,

restoring the written data of the memory cells into the sense amplifier circuits,

comparing first values of the reloaded data stored in the first latch circuits and second values of the restored data stored in the sense amplifier circuits, and

rewriting to each reloaded data to one of the memory cells connected one of the bit lines, respectively, when the first value is not same as the second value.

2. The device according to claim 1, wherein the control circuit controls the voltage generating circuit in such a manner that a maximum value of a write voltage at a time of the second verify write operation is less than a maximum value of a write voltage at a time of the first verify write operation.

3. The device according to claim 2, wherein the maximum value of the write voltage at the time of the second verify write operation is about ⅓

to ½

of the maximum value of the write voltage at the time of the first verify write operation.

4. The device according to claim 1, wherein the control circuit controls the voltage generating circuit in such a manner that a step-up width of a write voltage at a time of the second verify write operation is greater than a step-up width of a write voltage at a time of the first verify write operation.

5. The device according to claim 1, wherein the control circuit controls the voltage generating circuit in such a manner that a number of times of step-up at a time of the second verify write operation is less than a number of times of step-up at a time of the first verify write operation.

6. The device according to claim 1, wherein the memory cell array is an area which is capable of recording multi-bit data in each of the memory cells.

7. The device according to claim 1, further comprising a row decoder which selects a plurality of said word lines in the memory cell array, and applies a voltage.

8. The device according to claim 1, further comprising a column decoder which supplies data that is input from the data input/output terminal to a predetermined said first latch circuit in the data buffer.

9. The device according to claim 1, wherein the memory cell array includes first and second select transistors which are connected to one end and the other end of the current path of the memory cell string and select the memory cell string.

10. A write method of a semiconductor memory device, comprising:

executing a first verify write operation including

loading data from an input/output terminal to each of first latch circuits,

writing each loaded data in the first latch circuits to a memory cell connected one of bit lines, respectively,

reading the written data of the memory cells into the sense amplifier circuits, each of the sense amplifier circuits connected one of the bit lines, respectively,

verifying whether threshold voltages based on the written data are larger than a predetermined voltage, and

rewiring to a memory cell storing a written data having a threshold voltage which is smaller than the predetermined voltage; and

executing a second verify write operation including

reloading the data from the input/output terminal to each of the first latch circuits,

restoring the written data of the memory cells into the sense amplifier circuits,

comparing first values of the reloaded data stored in the first latch circuits and second values of the restored data stored in the sense amplifier circuits, and

rewriting to each reloaded data to one of the memory cells connected one of the bit lines, respectively, when the first value is not same as the second value.

11. The write method according to claim 10, wherein a maximum value of a write voltage at a time of the second verify write operation is less than a maximum value of a write voltage at a time of the first verify write operation.

12. The write method according to claim 10, wherein a step-up width of a write voltage at a time of the second verify write operation is greater than a step-up width of a write voltage at a time of the first verify write operation.

13. The write method according to claim 10, wherein a number of times of step-up at a time of the second verify write operation is less than a number of times of step-up at a time of the first verify write operation.

14. The write method according to claim 10, further comprising executing verify read from the memory cells after the second verify write operation is executed.

15. The write method according to claim 14, further comprising executing a third verify write operation including,

reloading the data from the input/output terminal to each of the first latch circuits

restoring the written data of the memory cells into the sense amplifier circuits,

comparing first values of the reloaded data stored in the first latch circuits and second values of the restored data stored in the sense amplifier circuits, and

rewriting to each reloaded data to one of the memory cells connected one of the bit lines, respectively, when the first value is not same as the second value.

16. A semiconductor memory device comprising:

a memory cell array having a plurality of memory cell strings arranged along a first direction respectively, each of the memory cell strings including a plurality of memory cells having current paths connected in series along a second direction which is perpendicular to the first direction, each of the memory cells having a charge accumulation layer and a control electrode, the control electrode extending in the first direction and connected to a memory cell located in an adjacent memory cell string;

a plurality of bit lines extending to the second direction, each of the bit lines electrically connected to one end of the current path of the associated memory cell string;

a source line extending in the first direction and electrically connected to the other end of the current paths of the memory cell strings;

a sense amplifier including a plurality of sense amplifier circuits, each of the sense amplifier circuit electrically connected to one of the bit lines, respectively;

a first date buffer including a plurality of first latch circuits, each of the first latch circuits electrically connected to one of the bit lines, respectively;

a second data buffer including a plurality of second latch circuits, each of the second latch circuits electrically connected to one of the first latch circuits, respectively; and

a control circuit executing a first verify write operation and a second verify write operation,

the first verify write operation including,

loading data from an external device to the first and second latch circuits,

writing each loaded data in the first latch circuits to one of the memory cells connected one of the bit lines, respectively,

reading the written data of the memory cells into the sense amplifier circuits,

verifying whether threshold voltages based on the written data are larger than a predetermined voltage, and

rewiring to a memory cell storing a written data having a threshold voltage which is smaller than the predetermined voltage; and

the second verify write operation including,

reloading the data from the second latch circuits to the first latch circuits,

restoring the written data of the memory cells into the sense amplifier circuits,

comparing first values of the reloaded data stored in the first latch circuits and second values of the restored data stored in the sense amplifier circuits, and

rewriting to each reloaded data to one of the memory cells connected one of the bit lines, respectively, when the first value is not same as the second value.

17. The device according to claim 16, wherein the control circuit controls the voltage generating circuit in such a manner that a maximum value of a write voltage at a time of the second verify write operation is less than a maximum value of a write voltage at a time of the first verify write operation.

18. The device according to claim 16, wherein the control circuit controls the voltage generating circuit in such a manner that a step-up width of a write voltage at a time of the second verify write operation is greater than a step-up width of a write voltage at a time of the first verify write operation.

19. The device according to claim 16, wherein the control circuit controls the voltage generating circuit in such a manner that a number of times of step-up at a time of the second verify write operation is less than a number of times of step-up at a time of the first verify write operation.

20. A write method of a semiconductor memory device, comprising:

executing a first verify write operation including

loading data to first latch circuits and second latch circuit,

writing each loaded data in the first latch circuits to a memory cell connected one of bit lines, respectively,

reading the written data of the memory cells into the sense amplifier circuits, each of the sense amplifier circuits connected one of the bit lines, respectively,

verifying whether threshold voltages based on the written data are larger than a predetermined voltage, and

rewiring to a memory cell storing a written data having a threshold voltage which is smaller than the predetermined voltage, and executing a second verify write operation including

reloading the data from the second latch circuit to the first latch circuits,

restoring the written data of the memory cells into the sense amplifier circuits,

comparing first values of the reloaded data stored in the first latch circuits and second values of the restored data stored in the sense amplifier circuits, and

rewriting to each reloaded data to one of the memory cells connected one of the bit lines, respectively, when the first value is not same as the second value.

21. The write method according to claim 20, further comprising executing verify read from the memory cells after the second verify write operation is executed.

22. The write method according to claim 20, further comprising:

executing a third verify write operation including,

reloading the data from the input/output terminal to each of the first latch circuits,

restoring the written data of the memory cells into the sense amplifier circuits,

comparing first values of the reloaded data stored in the first latch circuits and second values of the restored data stored in the sense amplifier circuits, and

rewriting to each reloaded data to one of the memory cells connected one of the bit lines, respectively, when the first value is not same as the second value.