Semiconductor device

• US 7,796,453 B2
• Filed: 06/24/2008
• Issued: 09/14/2010
• Est. Priority Date: 06/29/2007
• Status: Active Grant

• Current Assignee: Longitude Licensing Limited (Vector Capital Corporation)
• Original Assignee: Elpida Memory Incorporated (Micron Technology, Inc.)
• Inventors: Haraguchi, Yoshinori, Riho, Yoshiro, Oishi, Hayato, Matsui, Yoshinori
• Primary Examiner(s): TRAN, MICHAEL THANH
• Application Number:
  US12/145,240
• Publication Number:
  US 20090003107A1
• Time in Patent Office: 812 Days
• Field of Search: 365/203, 365/230.06
• US Class Current: 365/203
• CPC Class Codes: G11C 7/1048 Data bus control circuits, e.g. precharging, presetting, equalising
• CPC Class Codes: G11C 7/1051 Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
• CPC Class Codes: G11C 7/1069 I/O lines read out arrangements

Abstract

A semiconductor device includes a column decoder that generates a column selecting signal that selects any of a plurality of bit line pairs to which memory cells are connected according to a column address that is input; a bit line selecting switch that connects by the column selecting signal any of a plurality of bit line pairs and a data I/O line pair that outputs data that has been read from a memory cell to the outside; a data amplifier that amplifies a voltage differential of a data I/O line pair and outputs data that has been read to an output buffer; a data I/O line switch that is provided in the data I/O lines; an I/O line precharge circuit that precharges a data I/O line pair that is not on the side of the data amplifier; and an amplifier precharge circuit that precharges a data I/O line pair that is on the side of the data amplifier.

Claims

1. A semiconductor device comprising:

a data amplifier that amplifies a voltage differential of a data I/O line pair and outputs data that has been read to an output buffer;

a data I/O line switch that controls connection and disconnection between the data I/O line pair and the data amplifier;

an I/O line precharge circuit that precharges a first portion of the data I/O line pair, wherein the first portion of the data I/O line pair is separated by the data I/O line switch and located not on the side of the data amplifier;

an amplifier precharge circuit that precharges a second portion of the data I/O line pair, the second portion of the data I/O line pair is separated by the data I/O line switch and located on the side of the data amplifier;

a column decoder that generates a column selecting signal that selects a bit line pair from among a plurality of bit line pairs to which memory cells are connected according to a column address that is input; and

a bit line selecting switch that connects, according to the column selecting signal, the bit line pair of a plurality of the bit line pairs and a data I/O line pair that outputs data from a memory cell to the outside.

2. The semiconductor device according to claim 1 wherein, during a data reading period, the I/O line precharge circuit performs precharging of the first portion of the data I/O line pair in a period in which both of the bit line selecting switch and the data I/O line switch are in the OFF state.

3. The semiconductor device according to claim 1 wherein, during a data reading period, the amplifier precharge circuit performs precharging of the second portion of the data I/O line pair in a period in which the data I/O line switch is in the OFF state, and the bit line selecting switch is in the ON state.

4. The semiconductor device according to claim 1, further comprising:

a write amplifier that is connected to the second portion of the data I/O line pair and amplifies data that is input when writing to the memory cell,

wherein, during a data writing period, the I/O line precharge circuit performs precharging of the first portion of the data I/O line pair in a period in which the write amplifier is in the enabled state, and the data I/O line switch is in the OFF state.

5. The semiconductor device according to claim 1, wherein in the I/O line precharge circuit, a threshold voltage of a transistor that precharges the first portion of the data I/O line pair is set low compared to a threshold voltage of a transistor of the data I/O line switch.

6. The semiconductor device according to claim 1, wherein in the amplifier precharge circuit, a threshold voltage of a transistor that precharges the second portion of the data I/O line pair is set low compared to a threshold voltage of a transistor of the data I/O line switch.

7. The semiconductor device according to claim 1, wherein the precharge voltage that is precharged by the I/O line precharge circuit or the amplifier precharge circuit is set lower than the power supply voltage that is supplied from an external source.

8. A semiconductor device, comprising;

a first line;

a second line provided separately from the first line;

a switch circuit provided between the first line and the second line, the first and second lines being electrically disconnected from each other when the switch circuit is turned OFF and electrically connected to each other when the switch circuit is turned ON;

a first precharge circuit coupled to the first line to precharge, when activated, the first line;

a second precharge circuit coupled to the second line to precharge, when activated, the second line; and

an amplifier circuit coupled to the second line,

wherein the first precharge circuit being activated and the second precharge circuit being deactivated when the switch circuit is turned OFF and the amplifier circuit is activated, and the first precharge circuit being deactivated and the second precharge circuit being activated when the switch circuit is turned OFF and the amplifier circuit is deactivated.

9. The semiconductor device according to claim 8, further comprising:

a third line; and

a fourth line provided separately from the third line,

wherein the switch circuit is provided between the third line and the fourth line, the first precharge circuit is coupled to the third line, the second precharge circuit is coupled to the fourth line, and the amplifier circuit is coupled to the fourth line.

10. The semiconductor device according to claim 8, wherein the first precharge circuit is deactivated when the switch circuit is turned ON, and the amplifier circuit is activated.

11. The semiconductor device according to claim 8, wherein the second precharge circuit is deactivated when the switch circuit is turned ON, and the amplifier circuit is activated.

12. A semiconductor device, comprising:

first and second bit lines;

a sense amplifier circuit coupled to the bit lines to amplify a voltage difference between the first and second bit lines;

first and second I/O lines;

a bit line selecting switch provided between the first and second bit lines and the first and second I/O lines, and controlling connection and disconnection between the first and second I/O lines and the first and second bit lines;

an I/O precharge circuit coupled to the first and second I/O lines to precharge each of the first and second I/O lines;

a data amplifier circuit including first and second nodes to amplify a voltage difference between the first and second nodes;

a data I/O line switch provided between the first and second I/O lines and the first and second nodes of the data amplifier circuit, and controlling connection and disconnection between the first and second nodes and the first and second I/O lines; and

an amplifier precharge circuit coupled to the first and second nodes of the data amplifier circuit to precharge each of the first and second nodes.

13. The semiconductor device according to claim 12, wherein the first and second I/O lines include first and second local I/O lines and first and second data I/O lines respectively, the bit line selecting switch being provided between the first and second bit lines and the first and second local I/O lines, the data I/O line switch being provided between the first and second I/O lines and the first and second nodes of the data amplifier circuit, the semiconductor device further comprising a third switch circuit provided between the first and second local I/O lines and the first and second data I/O lines.

14. The semiconductor device according to claim 12, wherein the first precharge circuit precharges each of the first and second data I/O lines at a first voltage, and the second precharge circuit precharges each of the third and fourth data I/O lines at a second voltage which is substantially the same as the first voltage.

15. The semiconductor device according to claim 12, wherein the first precharge circuit includes a first transistor, and the second precharge circuit includes a second transistor, which is larger in threshold voltage than the first transistor.

16. The semiconductor device according to claim 15, wherein the second precharge circuit includes a third transistor, which is substantially the same in threshold voltage as the first transistor.

17. The semiconductor device according to claim 16, wherein each of the first, second, and third transistors comprises a p-channel type transistor.