Data flow control in multiple independent port
First Claim
1. A method for use in a memory device, comprising:
- receiving an input enable signal having an enable state and a disable state;
while the input enable signal is in the enable state;
receiving an input signal from external to the memory device;
outputting an output signal that is an echo of the input signal;
while the input enable signal is in the disable state;
outputting an output signal that is locally produced by the memory device,outputting an echo of the input enable signal.
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Accused Products
Abstract
A system includes a memory controller and a plurality of memory devices connected in-series that communicate with the memory controller. Each of the memory devices has multiple independent serial ports for receiving and transmitting data. The memory controller a device address (DA) or ID number for designating a device that executes a command. Data contained in the command sent by the memory controller is captured by an individual link control circuit, in response to internally generated clock with appropriate latencies. The captured data is written into a corresponding memory bank. The data stored in one of a plurality of memory banks of one memory device is read in accordance with the addresses issued by the memory controller. The read data is propagated from the memory device through the series-connected memory devices to the memory controller.
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Citations
17 Claims
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1. A method for use in a memory device, comprising:
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receiving an input enable signal having an enable state and a disable state; while the input enable signal is in the enable state; receiving an input signal from external to the memory device; outputting an output signal that is an echo of the input signal; while the input enable signal is in the disable state; outputting an output signal that is locally produced by the memory device, outputting an echo of the input enable signal. - View Dependent Claims (2, 3, 4)
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5. A memory device for use in an interconnection configuration including a plurality of memory devices connected in-series, the memory device comprising:
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a first input for receiving an input enable signal having an enable state and a disable state; a second input for receiving an input signal; a third input for receiving an output enable signal; a first output for outputting an output signal; a second output for outputting an echo of the input enable signal; a third output for outputting an echo of the output enable signal; a selector for, while the input enable signal is in the enable state, selecting the output signal to be an echo of the input signal, and while the input enable signal is in the disable state, selecting the output signal to be a locally produce signal. - View Dependent Claims (6, 7, 8, 9, 10)
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11. A method for use in a semiconductor device, comprising:
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receiving a chip select signal to produce a local chip select signal; receiving a reset signal to produce a local reset signal; receiving a clock signal and a complement of the clock signal; forwarding the clock signal while both the local reset signal is in an enable state and the local chip select signal is in an enable state; forwarding the complement of the clock signal while both the local reset signal is in the enable state and the local chip select signal is in the enable state; and producing an internal clock from one of the forwarded clock signal and the forwarded complement of the clock signal. - View Dependent Claims (12)
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13. An apparatus for controlling a semiconductor device, the apparatus comprising:
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a first input buffer for receiving and buffering a chip select signal to produce a local chip select signal; a second input buffer for receiving and buffering a reset signal to produce a local reset signal; a third input buffer for receiving and buffering a clock signal and forwards the clock signal while both the local reset signal is in an enable state and the local chip select signal is in an enable state; a fourth input buffer for receiving and buffering a complement of the clock signal while both the local reset signal is in an enable state and the local chip select signal is in an enable state; and an internal clock producer for producing an internal clock from one of the forwarded clock signal and the forwarded complement of the clock signal. - View Dependent Claims (14)
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15. A method comprising:
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receiving a chip select signal to produce a local chip select signal; receiving a reset signal to produce a local reset signal; receiving a clock signal and a complement of the dock signal; forwarding the clock signal while both the local reset signal is in an enable state and the local chip select signal is in an enable state; forwarding the complement of the clock signal while both the local reset signal is in the enable state and the local chip select signal is in the enable state; in a DDR (double data rate) mode of operation, generating an internal clock from both the clock signal and the complement of the dock signal. - View Dependent Claims (16, 17)
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Specification