Programmable asynchronous first-in-first-out (FIFO) structure with merging capability

• US 7,796,652 B2
• Filed: 04/27/2007
• Issued: 09/14/2010
• Est. Priority Date: 05/02/2006
• Status: Active Grant

• Current Assignee: Rambus Inc.
• Original Assignee: Diablo Technologies Incorporated (Rambus Inc.)
• Inventors: Pfaff, Dirk, Reitlingshoefer, Claus, Badalone, Riccardo
• Primary Examiner(s): Duong; Frank
• Application Number:
  US11/790,707
• Publication Number:
  US 20070258491A1
• Time in Patent Office: 1,236 Days
• Field of Search: 370/374, 370/412, 370/535
• US Class Current: 370/535
• CPC Class Codes: H04L 7/033 using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop

Abstract

Where high speed communication between a host and memory devices is carried over serial bit lanes, memory buffers are required for converting buffering the serial bit lanes, and for converting between serial and parallel formats. In addition, jitter, wander, and skew between the bit lanes need to be accommodated. The invention discloses a programmable asynchronous FIFO with the integrated ability to convert blocks of bits from serial to parallel as well as inserting bits from a parallel bus into the serial bit stream. The invention provides very low latency and can be implemented in low power technologies.

Claims

1. A first-in-first-out (FIFO) circuit for buffering of a high speed input bit stream of data bits (din_s), including:

a 1;

M demultiplexer for generating M lower speed serial input data streams (din_p1 to din_pM), the lower speed being M times slower than a speed of the high speed input bit stream, speed each lower speed serial input data stream carrying a distinct first subset of the data bits;

a first plurality M of 1;

N demultiplexers, each for generating N first data bit streams each first data bit stream carrying a distinct second subset of the first subset of the data bits;

a second plurality of M times N bit slices, each bit slice forwarding the first data bit streams into second data bit streams;

a third plurality M of N;

1 multiplexers, each for combining N second data bit streams of the second subset into a (lower speed) serial output bit stream (dop_p1 to dop_pM); and

an M;

1 multiplexer for combining the (lower speed) serial output bit streams into a high speed output bit stream (dop_s).

2. The FIFO as described in claim 1, wherein M=4 and N=3.

3. The FIFO as described in claim 1, further comprising a timing circuit (408) that provides a multi phase receive clock signal (rck_p1 to rck_pM);

and

wherein the 1;

M demultiplexer comprises a set of M edge triggered flip flops, each being clocked by a phase of the multi phase receive clock signal to periodically store one bit from the high speed input bit stream.

4. The FIFO as described in claim 3, wherein the timing circuit further provides a multi phase “

latch enable”

signal (lenX_pY); and

wherein the 1;

N demultiplexer comprises a set of N storage elements, each being enabled by a phase of the multi phase “

latch enable”

signal to periodically store one bit from one the lower speed serial input data streams.

5. The FIFO as described in claim 4, wherein the storage elements are transparent latches (1512).

6. The FIFO as described in claim 4, wherein the timing circuit further provides a multi phase “

clock enable”

signal (cenX_pY); and

wherein the N;

1 multiplexer comprises a set of N transmission gates (1536), each being enabled by a phase of the “

clock enable”

signal to periodically pass one data bit of the second subset into the (lower speed) serial output bit stream.

7. The FIFO as described in claim 6, wherein the timing circuit further provides a multi phase transmit clock signal (tck_pM) from which the multi phase “

clock enable”

signal is generated.

8. The FIFO as described in claim 7, wherein the N:

1 multiplexer further comprises a retiming flip flop (1550) for retiming the (lower speed) serial output bit stream, the retiming flip flop being clocked by a phase of the multi phase transmit clock signal.

9. The FIFO as described in claim 7, wherein the multi phase transmit clock signal is generated from a reference clock of a frequency that is related to the bit rate of the high speed input bit stream by a ratio of 1:

R.

10. The FIFO as described in claim 9, wherein the ratio R equals 1:

2.

11. The FIFO as described in claim 9, wherein each bit slice comprises a demux data alignment circuit (1804) for buffering the first data bit stream and outputting the buffered data bit stream on a Data Extraction highway (dData).

12. The FIFO as described in claim 11, wherein the demux data alignment circuit comprises one or more first clocked storage devices to insert a delay from the first data bit stream to the output of the demux data alignment circuit.

13. The FIFO as described in claim 12, wherein the first clocked storage devices in each bit slice are clocked individually with a phase of the multi phase “

clock enable”

signal chosen such that a parallel word of M times N bits is periodically output to the Data Extraction highway.

14. The FIFO as described in claim 9, wherein each bit slice further comprises:

a 2;

1 multiplexer (1802);

a merge data alignment circuit (1806) having a merge data input and an aligned merge data output;

and a merge enable alignment circuit (1808) having a merge enable input and an aligned merge enable output;

wherein the 2;

1 multiplexer selectively, under control of the aligned merge enable output, forwards either the first data bit stream or the aligned merge data output to the second data bit stream.

15. The FIFO as described in claim 14, wherein the merge data input receives a data bit from a Data Insertion highway (mData) and the merge enable input receives control bit from a Merge Control Highway (mEn).

16. The FIFO as described in claim 15, wherein the merge data alignment circuit and the merge enable alignment circuit in each bit slice each comprise one or more second clocked storage devices to insert a delay between their respective inputs and outputs.

17. The FIFO as described in claim 16, wherein the last of the second clocked storage devices in each bit slice are clocked individually with a phase of the multi phase “

clock enable”

signal chosen such that a parallel data word of M times N bits that is periodically input to the M times N merge data alignment circuits from the Data Insertion highway and the Merge Control Highway become substantially aligned with the first data bit streams.

18. A memory buffer serving a plurality C of serial bit lanes including a plurality C of channel slices (200), each channel slice serving one serial bit lane and comprising a first-in-first-out (FIFO) circuit for buffering of a high speed input bit stream of data bits (din_s), including:

a 1;

M demultiplexer for generating M lower speed serial input data streams (din_p1 to din_pM), the lower speed being M times slower than a speed of the high speed input bit stream, each lower speed serial input data stream carrying a distinct first subset of the data bits;

a first plurality M of 1;

N demultiplexers, each for generating N first data bit streams each first data bit stream carrying a distinct second subset of the first subset of the data bits;

a second plurality of M times N bit slices, each bit slice forwarding the first data bit streams into second data bit streams;

a third plurality M of N;

1 multiplexers, each for combining, N second data bit streams of the second subset into a (lower speed) serial output bit stream (dop_p1 to dop_pM); and

an M;

1 multiplexer for combining the (lower speed) serial output bit streams into a high speed output bit stream (dop_s).

19. The memory buffer described in claim 18, wherein:

the FIFO further comprises a timing circuit (408) that provides a multi phase receive clock signal (rck_p1 to rck_pM) and a multi phase “

latch enable”

signal (lenX_pY);

the 1;

M demultiplexer comprises a set of M edge triggered flip flops, each being clocked by a phase of the multi phase receive clock signal to periodically store one bit from the high speed input bit stream; and

the 1;

N demultiplexer comprises a set of N storage elements, each being enabled by a phase of the multi phase “

latch enable”

signal to periodically store one bit from one the lower speed serial input data streams.

20. The memory buffer described in claim 19, wherein:

the timing circuit further provides a multi phase “

clock enable”

signal (cenX_pY), a multi phase transmit clock signal (tck_pM) from which the multi phase “

clock enable”

signal is generated, the multi phase transmit clock signal being generated from a reference clock of a frequency that is related to the bit rate of the high speed input bit stream by a ratio of 1;

R; and

the N;

1 multiplexer comprises a set of N transmission gates (1536), each being enabled by a phase of the “

clock enable”

signal to periodically pass one data bit of the second subset into the (lower speed) serial output bit stream.

21. The memory buffer described in claim 20, wherein each Channel Slice further comprises:

a Data Extraction highway (dData);

a Data Insertion highway (mData); and

a Merge Control Highway (mEn),

and wherein each bit slice comprises;

a demux data alignment circuit (1804) for the purpose of buffering the first data bit stream and outputting it on the Data Extraction highway;

a 2;

1 multiplexer (1802);

a merge data alignment circuit (1806) having a merge data input connected to the Data Insertion highway and an aligned merge data output;

and

a merge enable alignment circuit (1808) having a merge enable input connected to the Merge Control highway, and an aligned merge enable output;

the 2;

1 multiplexer selectively, under control of the aligned merge enable output, forwarding either the first data bit stream or the aligned merge data output to the second data bit stream.

22. The memory buffer described in claim 21, wherein the demux data alignment circuit comprises one or more first clocked storage devices to insert a delay from the first data bit stream to the output of the demux data alignment circuit, the first clocked storage devices in each bit slice being clocked individually with a phase of the multi phase “

clock enable”

signal chosen such that a parallel word of M times N bits is periodically output to the Data Extraction highway.

23. The memory buffer described in claim 22, wherein the merge data alignment circuit and the merge enable alignment circuit in each bit slice each comprise one or more second clocked storage devices to insert a delay between their respective inputs and outputs, the second clocked storage devices in each bit slice being clocked individually with a phase of the multi phase “

clock enable”

signal chosen such that a parallel data word of M times N bits that is periodically input to the M times N merge data alignment circuits from the Data Insertion highway become substantially aligned with the first data bit streams.

24. A method for buffering a high speed input bit stream of data bits (din_s) performed in a memory buffer, including:

a first step of demultiplexing the input bit stream into M lower speed serial input data streams (din_p1 to din_pM), the lower speed being M times slower than a speed of the high speed input bit stream, each lower speed serial input data stream carrying a distinct first subset of the data bits;

a second step of demultiplexing each of the M lower speed serial input data streams into N first data bit stream each first data bit stream carrying a distinct second subset of the first subset of the data bits;

a step of bit slice processing comprising the step of forwarding the first data bit stream into the second data bit stream;

a first step of combining each group of N second data bit streams of the second subset into a serial output bit stream (dop_p1 to dop_pM); and

a second step of combining the (lower speed) serial output bit streams into a high speed output bit stream (dop_s.

25. The method as described in claim 24, wherein M=4 and N=3.

26. The method as described in claim 24, the first step of demultiplexing further including:

generating a multi phase receive clock signal (rck_p1 to rck_pM); and

periodically storing one bit from the input bit stream into one of M edge triggered flip flops, each flip flop being clocked by a phase of the multi phase receive clock signal.

27. The method as described in claim 26, the second step of demultiplexing further including:

generating a multi phase “

latch enable”

signal (lenX_pY); and

periodically storing one bit from each lower speed serial input data stream into one of N storage elements, each storage element being enabled by a phase of the multi phase “

latch enable”

signal.

28. The method as described in claim 27, the first step of combining further including:

generating a multi phase “

clock enable”

signal (cenX_pY); and

periodically passing one bit data bit of the second subset through a transmission gate into the (lower speed) serial output data stream, each transmission gate being enabled by a phase of the multi phase “

clock enable”

signal.

29. The method as described in claim 28, the step of generating a multi phase “

clock enable”

including generating a multi phase transmit clock signal (tck_pM) as the source of the multi phase “

clock enable”

signal.

30. The method as described in claim 29, the first step of combining further including retiming the (lower speed) serial output data stream in a retiming flip flop that is clocked by a phase of a multi phase transmit clock signal.

31. The method as described in claim 29, wherein the step of generating a multi phase transmit clock signal (tck_pM) includes synchronizing the multi phase transmit clock signal with a reference clock of a frequency that is related to the bit rate of the high speed input bit stream by a ratio of 1:

R.

32. The method as described in claim 31, including selecting the ratio R equals 1:

2.

33. The method as described in claim 31, the step of bit slice processing further comprising:

buffering the first data bit stream in an alignment buffer; and

outputting the buffered data bit stream on a Data Extraction highway (dData).

34. The method as described in claim 33, wherein the step of buffering comprises one or more steps of delaying the first data bit stream.

35. The method as described in claim 34, wherein the first of said one or more steps of delaying includes choosing a phase of the multi phase “

clock enable”

signal such that a parallel word of M times N bits is periodically output to the Data Extraction highway.

36. The method as described in claim 31, the step of bit slice processing further comprising:

aligning a merged data bit;

aligning a merge enable bit; and

provided the aligned merge enable bit is “

0”

, then forwarding the first data bit stream;

provided the aligned merge enable bit is other than “

0”

, forwarding the aligned merge data bit to the second data bit stream.

37. The method as described in claim 36, wherein the merged data bit is received from a Data Insertion highway (mData), and the merge enable bit is received from a Merge Control Highway (mEn).

38. The method as described in claim 37, wherein the each step of aligning comprises one or more steps of delaying.

39. The method as described in claim 37, wherein the last of the one or more steps of delaying includes individually choosing a phase of the multi phase “

clock enable”

signal such that parallel data words of M times N bits, comprising the merged data bits and the merge enable bits, which are periodically input from the Data Insertion highway and from the Merge Control highway, become substantially aligned with the first data bit streams.