Programmable asynchronous first-in-first-out (FIFO) structure with merging capability
First Claim
Patent Images
1. A first-in-first-out (FIFO) circuit for buffering of a high speed input bit stream of data bits (din_s), including:
- a 1;
M demultiplexer for generating M lower speed serial input data streams (din_p1 to din_pM), the lower speed being M times slower than a speed of the high speed input bit stream, speed each lower speed serial input data stream carrying a distinct first subset of the data bits;
a first plurality M of 1;
N demultiplexers, each for generating N first data bit streams each first data bit stream carrying a distinct second subset of the first subset of the data bits;
a second plurality of M times N bit slices, each bit slice forwarding the first data bit streams into second data bit streams;
a third plurality M of N;
1 multiplexers, each for combining N second data bit streams of the second subset into a (lower speed) serial output bit stream (dop_p1 to dop_pM); and
an M;
1 multiplexer for combining the (lower speed) serial output bit streams into a high speed output bit stream (dop_s).
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Abstract
Where high speed communication between a host and memory devices is carried over serial bit lanes, memory buffers are required for converting buffering the serial bit lanes, and for converting between serial and parallel formats. In addition, jitter, wander, and skew between the bit lanes need to be accommodated. The invention discloses a programmable asynchronous FIFO with the integrated ability to convert blocks of bits from serial to parallel as well as inserting bits from a parallel bus into the serial bit stream. The invention provides very low latency and can be implemented in low power technologies.
69 Citations
39 Claims
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1. A first-in-first-out (FIFO) circuit for buffering of a high speed input bit stream of data bits (din_s), including:
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a 1;
M demultiplexer for generating M lower speed serial input data streams (din_p1 to din_pM), the lower speed being M times slower than a speed of the high speed input bit stream, speed each lower speed serial input data stream carrying a distinct first subset of the data bits;a first plurality M of 1;
N demultiplexers, each for generating N first data bit streams each first data bit stream carrying a distinct second subset of the first subset of the data bits;a second plurality of M times N bit slices, each bit slice forwarding the first data bit streams into second data bit streams; a third plurality M of N;
1 multiplexers, each for combining N second data bit streams of the second subset into a (lower speed) serial output bit stream (dop_p1 to dop_pM); andan M;
1 multiplexer for combining the (lower speed) serial output bit streams into a high speed output bit stream (dop_s). - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17)
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18. A memory buffer serving a plurality C of serial bit lanes including a plurality C of channel slices (200), each channel slice serving one serial bit lane and comprising a first-in-first-out (FIFO) circuit for buffering of a high speed input bit stream of data bits (din_s), including:
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a 1;
M demultiplexer for generating M lower speed serial input data streams (din_p1 to din_pM), the lower speed being M times slower than a speed of the high speed input bit stream, each lower speed serial input data stream carrying a distinct first subset of the data bits;a first plurality M of 1;
N demultiplexers, each for generating N first data bit streams each first data bit stream carrying a distinct second subset of the first subset of the data bits;a second plurality of M times N bit slices, each bit slice forwarding the first data bit streams into second data bit streams; a third plurality M of N;
1 multiplexers, each for combining, N second data bit streams of the second subset into a (lower speed) serial output bit stream (dop_p1 to dop_pM); andan M;
1 multiplexer for combining the (lower speed) serial output bit streams into a high speed output bit stream (dop_s). - View Dependent Claims (19, 20, 21, 22, 23)
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24. A method for buffering a high speed input bit stream of data bits (din_s) performed in a memory buffer, including:
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a first step of demultiplexing the input bit stream into M lower speed serial input data streams (din_p1 to din_pM), the lower speed being M times slower than a speed of the high speed input bit stream, each lower speed serial input data stream carrying a distinct first subset of the data bits; a second step of demultiplexing each of the M lower speed serial input data streams into N first data bit stream each first data bit stream carrying a distinct second subset of the first subset of the data bits; a step of bit slice processing comprising the step of forwarding the first data bit stream into the second data bit stream; a first step of combining each group of N second data bit streams of the second subset into a serial output bit stream (dop_p1 to dop_pM); and a second step of combining the (lower speed) serial output bit streams into a high speed output bit stream (dop_s. - View Dependent Claims (25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39)
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Specification