Symmetrically and asymmetrically stacked transistor group RF switch

• US 7,796,969 B2
• Filed: 02/03/2006
• Issued: 09/14/2010
• Est. Priority Date: 10/10/2001
• Status: Active Grant

• Current Assignee: pSemi Corporation (Murata Manufacturing Co Limited)
• Original Assignee: Peregrine Semiconductor Corporation (Murata Manufacturing Co Limited)
• Inventors: Kelly, Dylan J., Burgener, Mark L.
• Primary Examiner(s): TIEU, BINH KIEN
• Application Number:
  US11/347,014
• Publication Number:
  US 20060194567A1
• Time in Patent Office: 1,684 Days
• Field of Search: 455/26.1, 455/78, 455/333, 455/425, 455/550.1, 455/556.1, 455/560, 257/280, 257/281, 257/341, 257/472
• US Class Current: 455/333
• CPC Class Codes: H02M 3/073 Charge pumps of the Schenkel-type
• CPC Class Codes: H03K 17/063 in field-effect transistor switches
• CPC Class Codes: H03K 17/6871 the output circuit comprising more than one controlled field-effect transistor
• CPC Class Codes: H03K 17/693 Switching arrangements with several input- or output-terminals, e.g. multiplexers, distributors logic circuits H03K19/00; code converters H03M5/00, H03M7/00

Abstract

A silicon-on-insulator (SOI) RF switch adapted for improved power handling capability using a reduced number of transistors is described. In one embodiment, an RF switch includes pairs of switching and shunting stacked transistor groupings to selectively couple RF signals between a plurality of input/output nodes and a common RF node. The switching and shunting stacked transistor groupings comprise one or more MOSFET transistors connected together in a “stacked” or serial configuration. In one embodiment, the transistor groupings are “symmetrically” stacked in the RF switch (i.e., the transistor groupings all comprise an identical number of transistors). In another embodiment, the transistor groupings are “asymmetrically” stacked in the RF switch (i.e., at least one transistor grouping comprises a number of transistors that is unequal to the number of transistors comprising at least one other transistor grouping). The stacked configuration of the transistor groupings enable the RF switch to withstand RF signals of varying and increased power levels. The asymmetrically stacked transistor grouping RF switch facilitates area-efficient implementation of the RF switch in an integrated circuit. Maximum input and output signal power levels can be withstood using a reduced number of stacked transistors.

Claims

1. An asymmetrically stacked transistor grouping RF switch circuit for switching RF signals, comprising:

a) at least one switch-shunt circuit controlled by a switch control signal, comprising;

(1) at least one switching transistor grouping controlled by the switch control signal, wherein the at least one switching transistor grouping comprises at least one switching stacked transistor grouping; and

(2) at least one shunting transistor grouping controlled by the switch control signal, wherein the at least one shunting transistor grouping comprises at least one shunting stacked transistor grouping;

wherein the stacked transistor groupings comprise one or more FETs arranged in a stacked configuration, wherein each of said FETs has a gate that is insulated from its channel, and wherein a number of FETs comprising at least one of the shunting transistor groupings is unequal to a number of FETs comprising at least one transistor grouping selected from the following;

     1) the at least one switching transistor grouping, and

     2) the at least one shunting transistor grouping.

2. The RF switch of claim 1, further comprising:

a) a first switching transistor grouping operatively coupled to selectively convey a first RF signal between a first node and an RF common node;

b) a first shunting transistor grouping operatively coupled to selectively convey the first RF signal between the first node and a ground;

c) a second switching transistor grouping operatively coupled to selectively convey a second RF signal between a second node and the RF common node; and

d) a second shunting transistor grouping operatively coupled to selectively convey the second RF signal between the second node and the ground;

wherein the first shunting transistor grouping comprises a number of FETs that is unequal to at least one of the following;

     1) a number of FETs comprising the first switching transistor grouping,

     2) a number of FETs comprising the second switching transistor grouping, and

     3) a number of FETs comprising the second shunting transistor grouping.

3. The RF switch of claim 2, wherein a first selected maximum voltage (RFvmax1) of the first RF signal is unequal to a second selected maximum voltage (RFvmax2) of the second RF signal, and wherein the number of FETs comprising the first shunting transistor grouping is selected such that the RVvmax1 divided by the number of FETs comprising the first shunting transistor grouping does not exceed a selected maximum FET source-to-drain voltage (SDvmax), and wherein the number of FETs comprising the second shunting transistor grouping is selected such that the RFvmax2 divided by the number of FETs comprising the second shunting transistor grouping does not exceed the SDvmax.

4. The RF switch of claim 1, wherein the RF switch comprises one of the following switch types:

a single-pole, single-throw switch;

a single-pole, multi-throw switch;

a multi-pole, single-throw switch; and

a multi-pole, multi-throw switch.

5. The RF switch of claim 1, wherein the switch circuit is fabricated using at least one of the following silicon-on-insulator (SOI) technologies:

SIMOX, bonded wafers having a thin silicon layer bonded to an insulating layer, silicon-on-sapphire, and ultrathin silicon-on-sapphire.

6. A symmetrically stacked transistor grouping RF switch circuit for switching RF signals, comprising:

a) at least one switch-shunt circuit controlled by a switch control signal, comprising;

(1) at least one switching transistor grouping controlled by the switch control signal, wherein the at least one switching transistor grouping comprises at least one switching stacked transistor grouping; and

(2) at least one shunting transistor grouping controlled by the switch control signal, wherein the at least one shunting transistor grouping comprises at least one shunting stacked transistor grouping;

wherein the stacked transistor groupings comprise one or more FETs arranged in a stacked configuration, wherein each of said FETs has a gate that is insulated from its channel, and wherein the switching and shunting stacked transistor groupings comprise an equal number of FETs, and wherein the number of FETs is determined by maximum power levels applied by the RF signals.

7. The RF switch of claim 6, further comprising:

a) a first switching transistor grouping operatively coupled to selectively convey a first RF signal between a first node and an RF common node;

b) a first shunting transistor grouping operatively coupled to selectively convey the first RF signal between the first node and a ground;

c) a second switching transistor grouping operatively coupled to selectively convey a second RF signal between a second node and the RF common node; and

d) a second shunting transistor grouping operatively coupled to selectively convey the second RF signal between the second node and the ground.

8. The RF switch of claim 6, wherein the RF switch comprises one of the following switch types:

a single-pole, single-throw switch;

a single-pole, multi-throw switch;

a multi-pole, single-throw switch; and

a multi-pole, multi-throw switch.

9. The RF switch of claim 6, wherein the switch circuit is fabricated using at least one of the following silicon-on-insulator (SOI) technologies:

SIMOX, bonded wafers having a thin silicon layer bonded to an insulating layer, silicon-on-sapphire, and ultrathin silicon-on-sapphire.

10. The RF switch of claim 6, wherein the RF signals have a selected maximum voltage (RFvmax), and wherein the number of FETs comprising the switching and shunting stacked transistor groupings is selected such that the RFvmax divided by the number of FETs does not exceed a selected maximum FET source-to-drain voltage (SDvmax).

11. An asymmetrically stacked transistor grouping RF switch circuit for switching RF signals, comprising:

(a) a first input port receiving a first RF input signal;

(b) a second input port receiving a second RF input signal;

(c) an RF common port;

(d) a first switch transistor grouping comprising a plurality of FETs arranged in a stacked configuration, wherein each of said FETs has a gate that is insulated from its channel, wherein said first switch transistor grouping has a first node coupled to the first input port and a second node coupled to the RF common port, and wherein the first switch transistor grouping is controlled by a switch control signal (SW);

(e) a second switch transistor grouping comprising a plurality of FETs arranged in a stacked configuration, wherein each of said FETs has a gate that is insulated from its channel, wherein said second transistor grouping has a first node coupled to the second input port and a second node coupled to the RF common port, and wherein the second switch transistor grouping is controlled by an inverse (SW_) of the switch control signal (SW);

(f) a first shunt transistor grouping comprising a plurality of FETs arranged in a stacked configuration, wherein each of said FETs has a gate that is insulated from its channel, wherein said first shunt transistor grouping has a first node coupled to the second input port and a second node coupled to ground, and wherein the first shunt transistor grouping is controlled by the switch control signal (SW); and

(g) a second shunt transistor grouping comprising a plurality of FETs arranged in a stacked configuration, wherein each of said FETs has a gate that is insulated from its channel, wherein said second shunt transistor grouping has a first node coupled to the first input port and a second node coupled to ground, wherein the second shunt transistor grouping is controlled by the inverse (SW_) of the switch control signal (SW);

wherein, when SW is enabled, the first switch and shunt transistor groupings are enabled while the second switch and shunt transistor groupings are disabled, thereby passing the first RF input signal through to the RF common port and shunting the second RF input signal to ground, and wherein when SW is disabled, the second switch and shunt transistor groupings are enabled while the first switch and shunt transistor groupings are disabled, thereby passing the second RF input signal through to the RF common port and shunting the first RF input signal to ground, and wherein a number of FETs comprising at least one of the shunt transistor groupings is unequal to a number of FETs comprising at least one transistor grouping selected from the following;

     1) the first switch transistor grouping,

     2) the second switch transistor grouping;

     3) the first shunt transistor grouping, and

     4) the second shunt transistor grouping.

12. The asymmetrically stacked transistor grouping RF switch circuit of claim 11, wherein the switch circuit is fabricated in a silicon-on-insulator (SOI) technology.

13. The RF switch circuit of claim 11, intended for switching RF signals having an operating period 1/Fo, wherein the gate of each FET has a capacitance Cg to its channel, and the gate is coupled to a control voltage via a gate resistor Rg having a value such that Rg*Cg>

1/Fo.

14. The RF switch circuit of claim 11, wherein the gate of each FET is coupled to a control voltage via a gate resistor Rg having a value of at least about 30 kΩ

.

15. The RF switch circuit of claim 12, wherein the circuit is designed for switching RF signals at an operating frequency Fo, the FETs are MOSFETs, the gate of each FET has a capacitance Cg to its channel, and the gate is coupled to a control voltage via a gate resistor Rg having a value such that Rg*Cg>

1/Fo.

16. The RF switch circuit of claim 15, wherein stacked MOSFETs of each transistor grouping share the signal voltage substantially equally without a need for ballast resistors parallel to a conduction path of such stacked MOSFETs, and wherein all Rg of the MOSFETs of each particular transistor grouping are commonly controlled by a corresponding switching voltage.

17. The RF switch circuit of claim 16, wherein gate resistors coupled to transistor gate nodes of the second switch and shunt transistor groupings are commonly coupled to the inverse switch control signal SW_.

18. The RF switch circuit of claim 11, wherein the FETs are MOSFETs having associated gate capacitance and an associated gate resistor coupling the gate to a drive signal, wherein RC time constants associated with each MOSFET within the transistor groupings are functions of the associated gate resistors and the associated gate capacitances, and wherein the RC time constant of each transistor far exceeds a period of the RF input signals thereby causing RF voltages to be shared equally across the MOSFETs.

19. The RF switch circuit of claim 11, wherein a breakdown voltage across the plurality of stacked MOSFET transistors of a selected transistor grouping is n times a breakdown voltage of an individual MOSFET transistor in the selected transistor grouping, wherein n comprises the total number of MOSFET transistors in the selected transistor grouping.

20. The RF switch circuit of claim 11, wherein the RF signals provided to the input ports may swing about a zero reference voltage.

21. The RF switch circuit of claim 15, wherein the first and second RF input signals have associated input power levels, and wherein increased input power levels can be accommodated by the RF switch circuit by increasing the number of MOSFET transistors per transistor grouping.

22. The RF switch circuit of claim 15, wherein the first and second RF input signals have associated input power levels, and wherein increased input power levels can be accommodated by the RF switch circuit by varying the physical size of the transistors used in implementing the transistor groupings.

23. A fully integrated RF switch circuit, comprising:

(a) the RF switch circuit as set forth in claim 11;

(b) a control logic block, coupled to the RF switch circuit, wherein the control logic block outputs the switch control signal (SW) and the inverse switch control signal (SW_); and

(c) a negative voltage generator, coupled to the control logic block, wherein the negative voltage generator receives a positive power supply voltage from an external power supply, and wherein the negative voltage generator outputs a negative power supply voltage.

24. A method of switching RF signals, comprising:

(a) inputting a first RF input signal to a first switch transistor grouping and a first shunt transistor grouping, wherein both the first switch and first shunt transistor groupings comprise a plurality of stacked FETs, each of which has a gate that is insulated from its channel;

(b) inputting a second RF input signal to a second switch transistor grouping and a second shunt transistor grouping, wherein both the second switch and second shunt transistor groupings comprise a plurality of stacked FETs, each of which has a gate that is insulated from its channel, wherein a number of FETs comprising at least one of the shunt transistor groupings is unequal to a number of FETs comprising at least one transistor grouping selected from the following;

     1) the first switch transistor grouping,

     2) the second switch transistor grouping;

     3) the first shunt transistor grouping, and

     4) the second shunt transistor grouping;

(c) enabling the first switch transistor grouping while disabling the first shunt transistor grouping, and simultaneously disabling the second switch transistor grouping while enabling the second shunt transistor grouping, thereby passing the first RF input signal and shunting the second RF input signal; and

, at exclusively alternative times; and

(d) enabling the second switch transistor grouping while disabling the second shunt transistor grouping, and simultaneously disabling the first switch transistor grouping while enabling the first shunt transistor grouping, thereby passing the second RF input signal and shunting the first RF input signal.

25. The method of claim 24, wherein the RF signals are expected to have a minimum operating frequency Fo, and wherein each FET has a gate capacitance Cg between its gate and its channel, and is coupled to a drive signal via an associated gate resistor Rg, the method further comprising ensuring that a product of Rg times Cg is greater than 1/Fo.

26. The method of claim 25, wherein the FETs are MOSFETs, and the method further comprises fabricating the switch circuit on a fully insulating sapphire wafer.

27. The method of claim 26, wherein the method further comprises fabricating the switch circuit on an Ultra-Thin-Silicon (“

UTSi”

) substrate.

28. The method of claim 24, wherein each FET is coupled to a drive signal via an associated gate resistor Rg having a value of at least about 30 kΩ

.

29. A symmetrically stacked transistor grouping RF switch circuit for switching RF signals, comprising:

(a) a first input port receiving a first RF input signal;

(b) a second input port receiving a second RF input signal;

(c) an RF common port;

(d) a first switch transistor grouping comprising a plurality of FETs arranged in a stacked configuration, wherein each of said FETs has a gate that is insulated from its channel, wherein said first switch transistor grouping has a first node coupled to the first input port and a second node coupled to the RF common port, and wherein the first switch transistor grouping is controlled by a switch control signal (SW);

(e) a second switch transistor grouping comprising a plurality of FETs arranged in a stacked configuration, wherein each of said FETs has a gate that is insulated from its channel, wherein said second transistor grouping has a first node coupled to the second input port and a second node coupled to the RF common port, and wherein the second switch transistor grouping is controlled by an inverse (SW_) of the switch control signal (SW);

(f) a first shunt transistor grouping comprising a plurality of FETs arranged in a stacked configuration, wherein each of said FETs has a gate that is insulated from its channel, wherein said first shunt transistor grouping has a first node coupled to the second input port and a second node coupled to ground, and wherein the first shunt transistor grouping is controlled by the switch control signal (SW); and

(g) a second shunt transistor grouping comprising a plurality of FETs arranged in a stacked configuration, wherein each of said FETs has a gate that is insulated from its channel, wherein said second shunt transistor grouping has a first node coupled to the first input port and a second node coupled to ground, wherein the second shunt transistor grouping is controlled by the inverse (SW_) of the switch control signal (SW);

wherein, when SW is enabled, the first switch and shunt transistor groupings are enabled while the second switch and shunt transistor groupings are disabled, thereby passing the first RF input signal through to the RF common port and shunting the second RF input signal to ground, and wherein when SW is disabled, the second switch and shunt transistor groupings are enabled while the first switch and shunt transistor groupings are disabled, thereby passing the second RF input signal through to the RF common port and shunting the first RF input signal to ground, and wherein the switch and shunt transistor groupings comprise an equal number of FETs, and wherein the number of FETs is determined by maximum power levels applied by the RF signals.

30. The RF switch circuit of claim 29, intended for switching RF signals having an operating period 1/Fo, wherein the gate of each FET has a capacitance Cg to its channel, and the gate is coupled to a control voltage via a gate resistor Rg having a value such that Rg*Cg>

1/Fo.