System and method for providing more logical memory ports than physical memory ports
First Claim
1. For a configurable integrated circuit (IC) that implements a user design having an associated user design clock cycle, said IC operating on a sub-cycle clock that has multiple sub-cycle periods within a user period of said user design clock cycle, a method of mapping the user design to the configurable IC, the method comprising:
- a) identifying accesses to multiple ports of a multi-port memory defined in the user design, said accesses being in a single user design clock cycle; and
b) mapping said accesses to the multiple ports of the multi-port memory to multiple accesses of a particular port of a physical memory in the configurable IC during multiple sub-cycles associated with the single user design clock cycle, wherein the particular port of the physical memory is for accessing the physical memory at least once per sub-cycle period, and the particular port comprises a clock input for receiving clock signals at a first frequency that is a frequency of the sub-cycle clock.
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Accused Products
Abstract
Some embodiments provide for a method of mapping a user design to a configurable integrated circuit (IC). The method is for a configurable IC that implements a user design with an associated user design clock cycle. The IC operates on a sub-cycle clock that has multiple sub-cycle periods within a user period of the user design clock cycle. The method identifies multiple port accesses to a first multi-port memory defined in the user design. The accesses are in a single user design clock cycle. The method maps the multiple port accesses to the first multi-port memory to multiple physical-port memory accesses to a second physical-port memory in the configurable IC during multiple sub-cycles associated with a single user design clock cycle.
205 Citations
17 Claims
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1. For a configurable integrated circuit (IC) that implements a user design having an associated user design clock cycle, said IC operating on a sub-cycle clock that has multiple sub-cycle periods within a user period of said user design clock cycle, a method of mapping the user design to the configurable IC, the method comprising:
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a) identifying accesses to multiple ports of a multi-port memory defined in the user design, said accesses being in a single user design clock cycle; and b) mapping said accesses to the multiple ports of the multi-port memory to multiple accesses of a particular port of a physical memory in the configurable IC during multiple sub-cycles associated with the single user design clock cycle, wherein the particular port of the physical memory is for accessing the physical memory at least once per sub-cycle period, and the particular port comprises a clock input for receiving clock signals at a first frequency that is a frequency of the sub-cycle clock. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A computer readable medium storing a computer program for mapping a user design having an associated user design clock cycle to a configurable integrated circuit (IC) that implements said user design, said configurable IC operating on a sub-cycle clock that has multiple sub-cycle periods within a user period of said user design clock cycle, said computer program comprising sets of instructions for:
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a) identifying multiple simultaneous accesses to a first multi-port memory defined in the user design through a particular number of ports of said first multi-port memory, said multiple simultaneous accesses being in a single user design clock cycle; and b) mapping said multiple simultaneous accesses to said first multi-port memory to multiple sequential accesses of a second physical-port memory in the configurable IC, through a smaller number of ports than the particular number of ports, during multiple sub-cycles associated with the single user design clock cycle, wherein a first physical port of said second physical-port memory is for accessing the second physical-port memory at least once per sub-cycle period, and the first physical port comprises a clock input for receiving clock signals at a first frequency that is a frequency of the sub-cycle clock. - View Dependent Claims (12, 13, 14, 15)
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16. A reconfigurable integrated circuit (IC) that implements a user design that is specified based on a user design clock cycle, said reconfigurable IC comprising:
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a) a physical memory with a physical memory port that operates at a frequency of a sub-cycle clock that is higher than a frequency of the user design clock cycle, wherein the physical memory port of said physical memory is for accessing the physical memory at least once per sub-cycle period, and the physical memory port comprises a clock input for receiving clock signals at the frequency of the sub-cycle clock; b) wherein said physical memory is accessible through said physical memory port multiple times per the user design clock cycle; and c) wherein said multiple times during said user design clock cycle correspond to accesses during a single period of the user design clock cycle of multiple memory ports of a multi-port memory in said user design. - View Dependent Claims (17)
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Specification