Virtual core management

• US 7,797,512 B1
• Filed: 10/31/2007
• Issued: 09/14/2010
• Est. Priority Date: 07/23/2007
• Status: Active Grant

• Current Assignee: Sun Microsystems Incorporated (Oracle Corporation), Sun Microsystems Technology Ltd. (Oracle Corporation)
• Original Assignee: Oracle America, Inc. (Oracle Corporation)
• Inventors: Puchol, Carlos, Cheng, Yu Qing, Favor, John Gregory, Song, Seungyoon Peter, Glaskowsky, Peter N., Moll, Laurent R.
• Primary Examiner(s): Coleman; Eric
• Application Number:
  US11/933,297
• Time in Patent Office: 1,049 Days
• Field of Search: None
• US Class Current: 712/10
• CPC Class Codes: G06F 9/455 Emulation; Interpretation; Software simulation, e.g. virtualisation or emulation of application or operating system execution engines
• CPC Class Codes: G06F 9/4825 Interrupt from clock, e.g. time of day
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A virtual core management system including one or more physical cores and one or more virtual cores. Each virtual core respectively includes a collection of logical states associated with execution of a corresponding program. The virtual core management system further includes one or more interrupt controllers configured to send one or more interrupt signals to interrupt execution of a corresponding program associated with at least one of the one or more virtual cores, and a virtual core management component configured to map the at least one virtual core to one of the one or more physical cores and route the one or more interrupt signals to the corresponding physical core.

Claims

1. A virtual core management system comprising:

one or more physical cores;

one or more virtual cores, each virtual core respectively including a collection of logical states associated with execution of a corresponding program;

one or more interrupt controllers configured to send one or more interrupt signals to interrupt execution of a corresponding program associated with at least one of the one or more virtual cores; and

a virtual core management component configured to map the at least one virtual core to one of the one or more physical cores and route the one or more interrupt signals to the corresponding physical core;

wherein the one or more interrupt controllers comprises one or more physical core interrupt controllers, and each of the one or more physical cores has a corresponding physical core interrupt controller.

2. The virtual core management system of claim 1, wherein the virtual core management component is configured to map at least one of the one or more interrupt signals to at least one of the one or more physical core interrupt controllers.

3. The virtual core management system of claim 1, wherein the one or more interrupt controllers comprises one or more virtual core interrupt controllers, and each of the one or more virtual cores has a corresponding virtual core interrupt controller.

4. The virtual core management system of claim 3, wherein at least one of the one or more virtual core interrupt controllers comprises a Programmable Interrupt Controller (PIC) that is configured to assign a priority level to one of the one or more interrupt signals.

5. The virtual core management system of claim 4, wherein the Programmable Interrupt Controller (PIC) comprises one or more of:

an Interrupt Request Register (IRR) configured to specify interrupts that are pending acknowledgement;

an In-Service Register (ISR) configured to specify interrupts that have been acknowledged but are waiting for an End Of Interrupt (EOI); and

an Interrupt Mask Register (IMR) configured to specify interrupts that are to be ignored and not acknowledged.

6. The virtual core management system of claim 1, wherein:

each of the one or more physical cores have corresponding registers; and

the virtual core management component is configured to map the at least one virtual core to one of the one or more physical cores by respectively transferring the one or more logical states of the at least one virtual core into the registers of the corresponding physical core.

7. A method adapted for use with a computer processor comprising one or more physical cores and one or more virtual cores, each virtual core respectively including a collection of logical states associated with execution of a corresponding program, the method comprising:

sending one or more interrupt signals to interrupt execution of a corresponding program associated with at least one of the one or more virtual cores; and

mapping the at least one virtual core to one of the one or more physical cores; and

routing the one or more interrupt signals to the corresponding physical core;

wherein one or more interrupt controllers are configured to send the one or more interrupt signals, and

wherein the interrupt controllers comprise one or more physical core interrupt controllers, and each of the one or more physical cores has a corresponding physical core interrupt controller.

8. The method of claim 7, wherein sending one or more interrupt signals includes sending one or more interrupt signals having a priority level.

9. The method of claim 7, wherein sending one or more interrupt signals includes one or more of:

specifying interrupts that are pending acknowledgement;

specifying interrupts that have been acknowledged but are waiting for an End Of Interrupt (EOI); and

specifying interrupts that are to be ignored and not acknowledged.

10. A computer readable medium that includes a program wherein the program causes a computer to perform a method comprising:

sending one or more interrupt signals to interrupt execution of a corresponding program associated with at least one of the one or more virtual cores;

mapping the at least one virtual core to one of the one or more physical cores; and

routing the one or more interrupt signals to the corresponding physical core;

wherein one or more interrupt controllers are configured to send the one or more interrupt signals, and

wherein the interrupt controllers comprise one or more physical core interrupt controllers, and each of the one or more physical cores has a corresponding physical core interrupt controller.

11. The computer readable medium of claim 10, wherein the virtual core management component is configured to map at least one of the one or more interrupt signals to at least one of the one or more physical core interrupt controllers.

12. The computer readable medium of claim 10, wherein the one or more interrupt controllers comprises one or more virtual core interrupt controllers, and each of the one or more virtual cores has a corresponding virtual core interrupt controller.

13. A virtual core management system comprising:

one or more physical cores;

means for providing one or more virtual cores, each virtual core respectively including a collection of logical states associated with execution of a corresponding program;

means for sending one or more interrupt signals to interrupt execution of a corresponding program associated with at least one of the one or more virtual cores; and

means for mapping the at least one virtual core to one of the one or more physical cores and routing the one or more interrupt signals to the corresponding physical core;

wherein the one or more interrupt controllers comprises one or more physical core interrupt controllers, and each of the one or more physical cores has a corresponding physical core interrupt controller.

14. The virtual core management system of claim 13, wherein the virtual core management component is configured to map at least one of the one or more interrupt signals to at least one of the one or more physical core interrupt controllers.

15. The virtual core management system of claim 13, wherein the one or more interrupt controllers comprises one or more virtual core interrupt controllers, and each of the one or more virtual cores has a corresponding virtual core interrupt controller.