Method for monitoring and adjusting circuit performance

• US 7,797,596 B2
• Filed: 09/26/2007
• Issued: 09/14/2010
• Est. Priority Date: 09/26/2007
• Status: Active Grant

• Current Assignee: Oracle America, Inc. (Oracle Corporation)
• Original Assignee: Oracle America, Inc. (Oracle Corporation)
• Inventors: Heald, Raymond A., Boyle, Steven R., Dixit, Anand
• Primary Examiner(s): Trimmings; John P
• Application Number:
  US11/861,403
• Publication Number:
  US 20090083598A1
• Time in Patent Office: 1,084 Days
• Field of Search: None
• US Class Current: 714/721
• CPC Class Codes: G01R 31/3187 Built-in tests

Abstract

A method for testing an integrated circuit implemented in an electronic system. The method includes placing an integrated circuit (or portion thereof) that is implemented in an operational system (e.g., in a computer system) in an offline status. An electrical parameter of the integrated system (e.g., a voltage, clock frequency, etc.) is set, and a built-in self-test (BIST) is conducted. Any failures that occur during the BIST are recorded. Testing is then repeated for each of a plurality of predetermined values of the electrical parameter, recording any failures that occur. Once testing is complete a failure rate/range is determined for each of the predetermined values.

Claims

1. A method for testing an integrated circuit implemented in an electronic system, the method comprising:

placing one or more functional blocks of the integrated circuit into an offline status;

setting an electrical parameter of the one or more functional blocks of the integrated circuit to a first of a plurality of predetermined values;

conducting a built-in self-test (BIST) of the one or more functional blocks of the integrated circuit;

recording any failures that occur while performing the BIST;

repeating said setting, said conducting, and said recording for each remaining one of the plurality of predetermined values of the electrical parameter;

determining a failure rate and a passing range for the BIST for each of the predetermined values;

predicting, for each of the plurality of predetermined values of the electrical parameter, a point in time at which the one or more functional blocks of the integrated circuit will fail based on the failure rates of the BIST; and

determining a new value of the electrical parameter at which the one or more functional blocks of the integrated circuit is to operate based on at least one of the failure rate and the passing range for the BIST.

2. The method as recited in claim 1, wherein the integrated circuit includes one or more PMOS (p-channel metal oxide semiconductor) devices, and wherein the electrical parameter is an n-well voltage.

3. The method as recited in claim 1, wherein the integrated circuit includes one or more NMOS (n-channel MOS) devices, and wherein the electrical parameter is a substrate voltage.

4. The method as recited in claim 1, wherein the BIST is a memory BIST, and wherein the integrated circuit comprises a memory.

5. The method as recited in claim 1, wherein the integrated circuit includes logic circuitry, and wherein the BIST is a logic BIST.

6. The method as recited in claim 1, wherein the electrical parameter is a clock frequency at which the integrated circuit operates, wherein the plurality of predetermined values of the electrical parameter comprise a plurality of different clock frequencies.

7. The method as recited in claim 6, further comprising coupling a frequency generator to the integrated circuit, wherein the plurality of different clock frequencies are provided by the frequency generator.

8. The method as recited in claim 6, wherein generating each of the plurality of different clock frequencies includes changing settings for one or more of a clock divider and a clock multiplier.

9. A method for testing an integrated circuit implemented in an electronic system, the method comprising:

placing one or more functional blocks of the integrated circuit into an offline status, wherein the one or more functional blocks of integrated circuit includes one or more PMOS (p-channel metal oxide semiconductor) devices;

setting an n-well voltage for the one or more PMOS devices to a first of a plurality of predetermined values;

conducting a built-in self-test (BIST) on the one or more functional blocks of the integrated circuit;

recording any failures that occur while performing the BIST;

repeating said setting, said conducting, and said recording for each remaining one of the plurality predetermined values of the n-well voltage;

determining a failure rate and a passing range for the BIST for each of the plurality of predetermined values;

predicting, for each of the predetermined values, a point in time at which the one or more functional blocks of the integrated circuit will fail based on the failure rates; and

determining at which of the plurality of predetermined values of the n-well voltage the one or more functional blocks of the integrated circuit is to operate subsequent to testing, based on the failure rates.

10. The method as recited in claim 9, wherein the integrated circuit includes a memory, and wherein the BIST is a memory BIST.

11. The method as recited in claim 9, wherein the integrated circuit includes logic circuitry, and wherein the BIST is a logic BIST.

12. A method for testing an integrated circuit implemented in an electronic system, the method comprising:

placing one or more functional blocks of the integrated circuit into an offline status, wherein the one or more functional blocks of the integrated circuit includes one or more NMOS (n-channel metal oxide semiconductor) devices;

setting substrate voltage for the one or more NMOS devices to a first of a plurality of predetermined values;

conducting a built-in self-test (BIST) on the one or more functional blocks of the integrated circuit;

recording any failures that occur while performing the BIST;

repeating said setting, said conducting, and said recording for each remaining one of the plurality predetermined values of the substrate voltage;

determining a failure rate and a passing range for the BIST for each of the plurality of predetermined values;

predicting, for each of the plurality of predetermined values, a point in time at which the one or more functional blocks of the integrated circuit will fail based on the failure rates and predetermined optimum operating conditions; and

further comprising determining at which of the plurality of predetermined values of the substrate voltage the integrated circuit is to operate subsequent to testing, based on the failure rates.

13. The method as recited in claim 12, wherein the integrated circuit includes a memory, and wherein the BIST is a memory BIST.

14. The method as recited in claim 12, wherein the integrated circuit includes logic circuitry, and wherein the BIST is a logic BIST.