Apparatus and method for merging data blocks with error correction code protection
First Claim
1. An apparatus having a computer-readable medium encoded with instruction executed within the apparatus for merging a first data block including first data, and a second data block including second data and an original Error Correction Code (ECC) having a plurality of ECC check bits, the apparatus comprising:
- a data unit enable module to identify data units of the first data to be merged into corresponding data units of the second data;
a data merge module arranged to merge the identified data units of the first data into the corresponding data units of the second data to create merged data; and
a plurality of check bit generation modules each comprising means for determining whether a state of a respective one of the ECC check bits differs from its original state in the original ECC in response to merging the identified data units, and for establishing a respective revised ECC check bit based on the determination, wherein the respective revised ECC check bits from the plurality of check bit generation modules collectively provide a merged ECC for the merged data.
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Accused Products
Abstract
An apparatus and method for selectively deriving Error Correction Codes (ECCs) or other data integrity information for integration into merged data blocks. First data is merged into second data that is error-protected using an ECC generated by a coding algorithm. Bytes or other data units are identified in the first data to be merged into the second data. It is determined whether each of the check bits of the ECC will differ from its original state in response to merging the first and second data. The check bits of the ECC that have been determined to differ from their respective original states are modified to create a “merged ECC.” The resulting data block includes the merged data and the merged ECC.
83 Citations
21 Claims
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1. An apparatus having a computer-readable medium encoded with instruction executed within the apparatus for merging a first data block including first data, and a second data block including second data and an original Error Correction Code (ECC) having a plurality of ECC check bits, the apparatus comprising:
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a data unit enable module to identify data units of the first data to be merged into corresponding data units of the second data; a data merge module arranged to merge the identified data units of the first data into the corresponding data units of the second data to create merged data; and a plurality of check bit generation modules each comprising means for determining whether a state of a respective one of the ECC check bits differs from its original state in the original ECC in response to merging the identified data units, and for establishing a respective revised ECC check bit based on the determination, wherein the respective revised ECC check bits from the plurality of check bit generation modules collectively provide a merged ECC for the merged data. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. An apparatus having a computer-readable medium encoded with instruction executed within the apparatus for merging a first data block including first data, and a second data block including second data and an original Error Correction Code (ECC) having a plurality of ECC check bits, the apparatus comprising:
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merging means for merging one or more data units of the first data into corresponding data units of the second data to create merged data; determining means for determining whether one or more of the check bits of the original ECC will change as a result of the merging of the one or more data units of the first data into the second data; and modifying means coupled to the determining means for modifying one or more of the check bits of the original ECC to produce a modified ECC for the merged data, in response to a determination by the determining means that a corresponding one or more of the check bits of the original ECC will change. - View Dependent Claims (12, 13)
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14. A method having a computer-readable medium encoded with instruction executed within a programmable computer for merging first data of a first data block into second data of a second data block, the second data block including a plurality of check bits generated according to a coding algorithm and forming an Error Correction Code (ECC) for the second data, the method comprising:
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specifying one or more data units of the second data to be replaced by a corresponding one or more data units of the first data; determining, as a function of the coding algorithm, whether each of the check bits of the ECC will differ from its respective original state upon replacing the specified data units of the second data; modifying the check bits of the ECC that have been determined to differ from their respective original states to create a merged ECC; replacing the specified data units of the second data with the corresponding one or more data units of the first data to create merged data; and creating a resultant data block including the merged data and the merged ECC. - View Dependent Claims (15, 16, 17, 18, 19, 20)
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21. An apparatus having a computer-readable medium encoded with instruction executed within the apparatus for updating one or more check bits of an Error Correction Code (ECC) associated with reference data, in response to merging one or more data units of modifying data with the reference data, comprising:
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a data unit enable module configured to store a plurality of enable bits, one for each of a first number of data units associated with the reference data, wherein the enable bits include one or more active enable bits identifying data units of the modifying data to be merged with the reference data; a plurality of check bit generation modules, one for each of the check bits of the ECC associated with the reference data, wherein each of the plurality of check bit generation modules comprises; a first stage array coupled to receive a set of corresponding data bits of the modifying data and the reference data according to a coding algorithm used to generate the ECC of the reference data, and to output a second number of change indications each indicating whether the merging of the one or more data units of modifying data with the reference data for a respective one of the first number of data units warrants a change in the check bit; a gating array coupled to the first stage array to receive the second number of change indications and coupled to the data unit enable module to receive the plurality of enable bits, and arranged to pass the change indications associated with the active enable bits; a second stage array coupled to the gating array to receive the change indications passed by the gating array, and arranged to generate a collective change indication; and a third stage array coupled to the second stage array to receive the collective change indication and coupled to receive a corresponding one of the check bits of the ECC associated with the reference data, and arranged to modify the corresponding one of the check bits of the ECC based on the collective change indication.
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Specification