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Method for manufacturing a CMOS device having dual metal gate

  • US 7,799,630 B2
  • Filed: 01/23/2008
  • Issued: 09/21/2010
  • Est. Priority Date: 01/23/2008
  • Status: Active Grant
First Claim
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1. A method for manufacturing a CMOS device having dual metal gate comprising steps of:

  • providing a substrate having a first conductive type transistor, a second conductive type transistor, and a dielectric layer covering the first conductive type transistor and the second conductive type transistor formed thereon;

    planarizing the dielectric layer to expose gate conductive layers of a first gate of the first conductive type transistor and of a second gate of the second conductive type transistor;

    forming a patterned blocking layer covering the second conductive type transistor and exposing the first conductive type transistor on the substrate;

    performing a first etching process to remove the gate conductive layer of the first gate to form a first opening;

    sequentially forming a first metal layer and a second metal layer in the first opening; and

    removing the patterned blocking layer covering the second conductive type transistor after forming the first metal layer and the second metal layer.

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