Method for manufacturing a CMOS device having dual metal gate
First Claim
1. A method for manufacturing a CMOS device having dual metal gate comprising steps of:
- providing a substrate having a first conductive type transistor, a second conductive type transistor, and a dielectric layer covering the first conductive type transistor and the second conductive type transistor formed thereon;
planarizing the dielectric layer to expose gate conductive layers of a first gate of the first conductive type transistor and of a second gate of the second conductive type transistor;
forming a patterned blocking layer covering the second conductive type transistor and exposing the first conductive type transistor on the substrate;
performing a first etching process to remove the gate conductive layer of the first gate to form a first opening;
sequentially forming a first metal layer and a second metal layer in the first opening; and
removing the patterned blocking layer covering the second conductive type transistor after forming the first metal layer and the second metal layer.
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Abstract
A method for manufacturing a CMOS device having dual metal gate includes providing a substrate having at least two transistors of different conductive types and a dielectric layer covering the two transistors, planarizing the dielectric layer to expose gate conductive layers of the two transistors, forming a patterned blocking layer exposing one of the conductive type transistor, performing a first etching process to remove a portion of a gate of the conductive type transistor, reforming a metal gate, removing the patterned blocking layer, performing a second etching process to remove a portion of a gate of the other conductive type transistor, and reforming a metal gate.
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Citations
55 Claims
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1. A method for manufacturing a CMOS device having dual metal gate comprising steps of:
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providing a substrate having a first conductive type transistor, a second conductive type transistor, and a dielectric layer covering the first conductive type transistor and the second conductive type transistor formed thereon; planarizing the dielectric layer to expose gate conductive layers of a first gate of the first conductive type transistor and of a second gate of the second conductive type transistor; forming a patterned blocking layer covering the second conductive type transistor and exposing the first conductive type transistor on the substrate; performing a first etching process to remove the gate conductive layer of the first gate to form a first opening; sequentially forming a first metal layer and a second metal layer in the first opening; and removing the patterned blocking layer covering the second conductive type transistor after forming the first metal layer and the second metal layer. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20)
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21. A method for manufacturing a CMOS device having dual metal gate comprising steps of:
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providing a substrate having a first conductive type transistor, a second conductive type transistor, and a dielectric layer covering the first conductive type transistor and the second conductive type transistor formed thereon; planarizing the dielectric layer to expose gate conductive layers of a first gate of the first conductive type transistor and of a second gate of the second conductive type transistor; forming a patterned blocking layer covering the second conductive type transistor and exposing the first conductive type transistor on the substrate, the patterned blocking layer comprising at least a silicon oxide layer and a silicon nitride layer; performing a first etching process to remove the gate conductive layer of the first gate to form a first opening; sequentially forming a first metal layer and a second metal layer in the first opening; and removing the patterned blocking layer covering the second conductive type transistor. - View Dependent Claims (22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38)
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39. A method for manufacturing a CMOS device having dual metal gate comprising steps of:
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providing a substrate having a first conductive type transistor, a second conductive type transistor, and a dielectric layer covering the first conductive type transistor and the second conductive type transistor formed thereon; planarizing the dielectric layer to expose gate conductive layers of a first gate of the first conductive type transistor and of a second gate of the second conductive type transistor; forming a patterned blocking layer covering the second conductive type transistor and exposing the first conductive type transistor on the substrate, the patterned blocking layer comprising amorphous carbon (APF); performing a first etching process to remove the gate conductive layer of the first gate to form a first opening; sequentially forming a first metal layer and a second metal layer in the first opening; and removing the patterned blocking layer covering the second conductive type transistor. - View Dependent Claims (40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55)
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Specification