Method for manufacturing a CMOS device having dual metal gate

• US 7,799,630 B2
• Filed: 01/23/2008
• Issued: 09/21/2010
• Est. Priority Date: 01/23/2008
• Status: Active Grant

• Current Assignee: United Microelectronics Corporation
• Original Assignee: United Microelectronics Corporation
• Inventors: Ma, Guang-Hwa, Cheng, Li-Wei, Chiang, Tian-Fu, Yu, Chih-Hao, Hsu, Che-Hua, Lin, Chien-Ting, Chou, Cheng-Hsien
• Primary Examiner(s): COLEMAN, WILLIAM D
• Application Number:
  US12/018,214
• Publication Number:
  US 20090186458A1
• Time in Patent Office: 972 Days
• Field of Search: 438/230, 438/283, 438/573, 438/652, 257/E21.474
• US Class Current: 438/230
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823842 gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
• CPC Class Codes: H01L 29/4966 the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2 H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/7833 with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/7843 the means being an applied insulating layer

Abstract

A method for manufacturing a CMOS device having dual metal gate includes providing a substrate having at least two transistors of different conductive types and a dielectric layer covering the two transistors, planarizing the dielectric layer to expose gate conductive layers of the two transistors, forming a patterned blocking layer exposing one of the conductive type transistor, performing a first etching process to remove a portion of a gate of the conductive type transistor, reforming a metal gate, removing the patterned blocking layer, performing a second etching process to remove a portion of a gate of the other conductive type transistor, and reforming a metal gate.

Claims

1. A method for manufacturing a CMOS device having dual metal gate comprising steps of:

providing a substrate having a first conductive type transistor, a second conductive type transistor, and a dielectric layer covering the first conductive type transistor and the second conductive type transistor formed thereon;

planarizing the dielectric layer to expose gate conductive layers of a first gate of the first conductive type transistor and of a second gate of the second conductive type transistor;

forming a patterned blocking layer covering the second conductive type transistor and exposing the first conductive type transistor on the substrate;

performing a first etching process to remove the gate conductive layer of the first gate to form a first opening;

sequentially forming a first metal layer and a second metal layer in the first opening; and

removing the patterned blocking layer covering the second conductive type transistor after forming the first metal layer and the second metal layer.

2. The method of claim 1 further comprising steps for forming the first conductive type transistor and the second conductive type transistor:

sequentially forming a gate dielectric layer, the gate conductive layer, and a patterned hard mask layer on the substrate;

performing an etching process to etch the gate conductive layer and the gate dielectric layer through the patterned hard mask layer to form the first gate and the second gate respectively;

forming a first light doped drain (LDD) and a second LDD in the substrate at two sides of the first gate and the second gate, respectively;

forming a spacer on sidewalls of the first gate and the second gate, respectively; and

forming a first source/drain and a second source/drain in the substrate at two sides of the first gate and the second gate, respectively.

3. The method of claim 1, wherein the step of planarizing the dielectric layer comprises a chemical mechanical polishing (CMP) process and an etching back process.

4. The method of claim 1, wherein the patterned blocking layer is a multi-layer.

5. The method of claim 1, wherein the patterned blocking layer comprise amorphous carbon (APF).

6. The method of claim 1, wherein the first metal layer comprises MoAlN, W, MoN, TaCNO, or WN.

7. The method of claim 1 further comprising a step of removing the first metal layer and the second metal layer covering the second conductive type transistor performed after forming the first metal layer and the second metal layer.

8. The method of claim 1, wherein the dielectric layer serves as an inter-layer dielectric (ILD) layer.

9. The method of claim 2 further comprising a step of performing a salicide process to form salicide layers respectively on surfaces of the first source/drain and the second source drain after forming the first conductive type transistor and the second conductive type transistor.

10. The method of claim 2 further comprising steps of:

performing a second etching process to remove the gate conductive layer of the second gate to form a second opening; and

sequentially forming a third metal layer and a fourth metal layer in the second opening.

11. The method of claim 10 further comprising steps of:

performed a third etching process and a fourth etching process respectively after the first etching process and the second etching process for removing the gate dielectric layer; and

forming a high-K gate dielectric layer in the first opening and a high-K gate dielectric layer in the second opening respectively after the third etching process and the fourth etching process.

12. The method of claim 10, wherein the gate dielectric layer is a high-K gate dielectric layer.

13. The method of claim 10, wherein the third metal layer comprises TaC.

14. The method of claim 10, wherein the second metal layer and the fourth metal layer respectively comprise Al, Ti, Ta, W, Nb, Mo, TiN, TiC, TaN, Ti/W, or Ti/TiN.

15. The method of claim 10 further comprising a step of performing a planarization process to remove unnecessary first metal layer, second metal layer, third metal layer, and the fourth metal layer after forming the fourth metal layer.

16. The method of claim 12, wherein the high-K gate dielectric layers are exposed at bottoms of the first opening and the second opening respectively after the first etching process and second etching process.

17. The method of claim 15 further comprising a step of removing the dielectric layer after the planarization process.

18. The method of claim 17 further comprising a step of forming a contact hole etch stop layer (CESL) on the substrate after removing the dielectric layer.

19. The method of claim 4, wherein the patterned blocking layer comprises at least a silicon oxide layer and a silicon nitride layer.

20. The method of claim 19, wherein a ratio between a thickness of the silicon oxide layer and a thickness of the silicon nitride layer is about 1:

3.

21. A method for manufacturing a CMOS device having dual metal gate comprising steps of:

providing a substrate having a first conductive type transistor, a second conductive type transistor, and a dielectric layer covering the first conductive type transistor and the second conductive type transistor formed thereon;

planarizing the dielectric layer to expose gate conductive layers of a first gate of the first conductive type transistor and of a second gate of the second conductive type transistor;

forming a patterned blocking layer covering the second conductive type transistor and exposing the first conductive type transistor on the substrate, the patterned blocking layer comprising at least a silicon oxide layer and a silicon nitride layer;

performing a first etching process to remove the gate conductive layer of the first gate to form a first opening;

sequentially forming a first metal layer and a second metal layer in the first opening; and

removing the patterned blocking layer covering the second conductive type transistor.

22. The method of claim 21 further comprising steps for forming the first conductive type transistor and the second conductive type transistor:

sequentially forming a gate dielectric layer, the gate conductive layer, and a patterned hard mask layer on the substrate;

performing an etching process to etch the gate conductive layer and the gate dielectric layer through the patterned hard mask layer to form the first gate and the second gate respectively;

forming a first light doped drain (LDD) and a second LDD in the substrate at two sides of the first gate and the second gate, respectively;

forming a spacer on sidewalls of the first gate and the second gate, respectively; and

forming a first source/drain and a second source/drain in the substrate at two sides of the first gate and the second gate, respectively.

23. The method of claim 22 further comprising a step of performing a salicide process to form salicide layers respectively on surfaces of the first source/drain and the second source drain after forming the first conductive type transistor and the second conductive type transistor.

24. The method of claim 22 further comprising steps of:

performing a second etching process to remove the gate conductive layer of the second gate to form a second opening; and

sequentially forming a third metal layer and a fourth metal layer in the second opening.

25. The method of claim 21, wherein the step of planarizing the dielectric layer comprises a chemical mechanical polishing (CMP) process and an etching back process.

26. The method of claim 21, wherein the patterned blocking layer is a multi-layer.

27. The method of claim 21, wherein a ratio between a thickness of the silicon oxide layer and a thickness of the silicon nitride layer is about 1:

3.

28. The method of claim 21, wherein the first metal layer comprises MoAlN, W, MoN, TaCNO, or WN.

29. The method of claim 21 further comprising a step of removing the first metal layer and the second metal layer covering the second conductive type transistor performed after forming the first metal layer and the second metal layer.

30. The method of claim 21, wherein the dielectric layer serves as an inter-layer dielectric (ILD) layer.

31. The method of claim 24 further comprising steps of:

performed a third etching process and a fourth etching process respectively after the first etching process and the second etching process for removing the gate dielectric layer; and

forming a high-K gate dielectric layer in the first opening and a high-K gate dielectric layer in the second opening respectively after the third etching process and the fourth etching process.

32. The method of claim 24, wherein the gate dielectric layer is a high-K gate dielectric layer.

33. The method of claim 32, wherein the high-K gate dielectric layers are exposed at bottoms of the first opening and the second opening respectively after the first etching process and second etching process.

34. The method of claim 24, wherein the third metal layer comprises TaC.

35. The method of claim 24, wherein the second metal layer and the fourth metal layer respectively comprise Al, Ti, Ta, W, Nb, Mo, TiN, TiC, TaN, Ti/W, or Ti/TiN.

36. The method of claim 24 further comprising a step of performing a planarization process to remove unnecessary first metal layer, second metal layer, third metal layer, and the fourth metal layer after forming the fourth metal layer.

37. The method of claim 36 further comprising a step of removing the dielectric layer after the planarization process.

38. The method of claim 37 further comprising a step of forming a contact hole etch stop layer (CESL) on the substrate after removing the dielectric layer.

39. A method for manufacturing a CMOS device having dual metal gate comprising steps of:

providing a substrate having a first conductive type transistor, a second conductive type transistor, and a dielectric layer covering the first conductive type transistor and the second conductive type transistor formed thereon;

planarizing the dielectric layer to expose gate conductive layers of a first gate of the first conductive type transistor and of a second gate of the second conductive type transistor;

forming a patterned blocking layer covering the second conductive type transistor and exposing the first conductive type transistor on the substrate, the patterned blocking layer comprising amorphous carbon (APF);

performing a first etching process to remove the gate conductive layer of the first gate to form a first opening;

sequentially forming a first metal layer and a second metal layer in the first opening; and

removing the patterned blocking layer covering the second conductive type transistor.

40. The method of claim 39 further comprising steps for forming the first conductive type transistor and the second conductive type transistor:

sequentially forming a gate dielectric layer, the gate conductive layer, and a patterned hard mask layer on the substrate;

performing an etching process to etch the gate conductive layer and the gate dielectric layer through the patterned hard mask layer to form the first gate and the second gate respectively;

forming a first light doped drain (LDD) and a second LDD in the substrate at two sides of the first gate and the second gate, respectively;

forming a spacer on sidewalls of the first gate and the second gate, respectively; and

forming a first source/drain and a second source/drain in the substrate at two sides of the first gate and the second gate, respectively.

41. The method of claim 40 further comprising steps of:

performing a second etching process to remove the gate conductive layer of the second gate to form a second opening; and

sequentially forming a third metal layer and a fourth metal layer in the second opening.

42. The method of claim 39, wherein the step of planarizing the dielectric layer comprises a chemical mechanical polishing (CMP) process and an etching back process.

43. The method of claim 39, wherein the patterned blocking layer is a multi-layer.

44. The method of claim 39, wherein the first metal layer comprises MoAlN, W, MoN, TaCNO, or WN.

45. The method of claim 39 further comprising a step of removing the first metal layer and the second metal layer covering the second conductive type transistor performed after forming the first metal layer and the second metal layer.

46. The method of claim 39, wherein the dielectric layer serves as an inter-layer dielectric (ILD) layer.

47. The method of claim 40 further comprising a step of performing a salicide process to form salicide layers respectively on surfaces of the first source/drain and the second source drain after forming the first conductive type transistor and the second conductive type transistor.

48. The method of claim 41 further comprising steps of:

performed a third etching process and a fourth etching process respectively after the first etching process and the second etching process for removing the gate dielectric layer; and

forming a high-K gate dielectric layer in the first opening and a high-K gate dielectric layer in the second opening respectively after the third etching process and the fourth etching process.

49. The method of claim 41, wherein the gate dielectric layer is a high-K gate dielectric layer.

50. The method of claim 41, wherein the third metal layer comprises TaC.

51. The method of claim 41, wherein the second metal layer and the fourth metal layer respectively comprise Al, Ti, Ta, W, Nb, Mo, TiN, TiC, TaN, Ti/W, or Ti/TiN.

52. The method of claim 41 further comprising a step of performing a planarization process to remove unnecessary first metal layer, second metal layer, third metal layer, and the fourth metal layer after forming the fourth metal layer.

53. The method of claim 49, wherein the high-K gate dielectric layers are exposed at bottoms of the first opening and the second opening respectively after the first etching process and second etching process.

54. The method of claim 52 further comprising a step of removing the dielectric layer after the planarization process.

55. The method of claim 54 further comprising a step of forming a contact hole etch stop layer (CESL) on the substrate after removing the dielectric layer.