Ruthenium alloy film for copper interconnects

• US 7,799,674 B2
• Filed: 05/29/2008
• Issued: 09/21/2010
• Est. Priority Date: 02/19/2008
• Status: Active Grant

• Current Assignee: ASM Japan K.K. (ASM International NV)
• Original Assignee: ASM Japan K.K. (ASM International NV)
• Inventors: Inoue, Hiroaki, Shinriki, Hiroshi
• Primary Examiner(s): Nguyen; Ha Tran T
• Assistant Examiner(s): BROWN, VALERIE N
• Application Number:
  US12/129,345
• Publication Number:
  US 20090209101A1
• Time in Patent Office: 845 Days
• Field of Search: 438625-629, 438/637, 438642-644, 438/650, 438/658, 438/676, 438/680, 438686-687
• US Class Current: 438/627
• CPC Class Codes: C23C 16/32 Carbides
• CPC Class Codes: C23C 16/34 Nitrides C23C16/303 takes precedence
• CPC Class Codes: C23C 16/36 Carbonitrides
• CPC Class Codes: C23C 16/45531 specially adapted for making ternary or higher compositions
• CPC Class Codes: H01L 21/28562 Selective deposition
• CPC Class Codes: H01L 21/76843 formed in openings in a dielectric
• CPC Class Codes: H01L 21/76846 Layer combinations
• CPC Class Codes: H01L 21/76876 for deposition from the gas phase, e.g. CVD
• CPC Class Codes: H01L 21/76877 Filling of holes, grooves or trenches, e.g. vias, with conductive material
• CPC Class Codes: H01L 23/53238 Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A method for forming interconnect wiring, includes: (i) covering a surface of a connection hole penetrating through interconnect dielectric layers formed on a substrate for interconnect wiring, with an underlying alloy layer selected from the group consisting of an alloy film containing ruthenium (Ru) and at least one other metal atom (M), a nitride film thereof, a carbide film thereof, and an nitride-carbide film thereof, and (ii) filling copper or a copper compound in the connection hole covered with the underlying layer.

Claims

1. A method for forming interconnect wiring, comprising:

(i) covering a surface of a connection hole penetrating through interconnect dielectric layers formed on a substrate for interconnect wiring, with an underlying alloy layer selected from the group consisting of a film of an alloy containing ruthenium (Ru) and at least one other metal atom (M) wherein M is Ti or Ta, a nitride film of the alloy, a carbide film of the alloy, and a nitride-carbide film of the alloy, by atomic layer deposition comprising supplying a Ru precursor and an M precursor alternately in cycles wherein the Ru precursor is supplied in two pulses per one pulse of the M precursor supplied in one cycle; and

(ii) filling copper or a copper compound by CVD into at least a part of the connection hole covered with the underlying alloy layer.

2. The method according to claim 1, further comprising covering a surface of the connection hole with a copper diffusion barrier layer prior to step (i).

3. The method according to claim 2, wherein the barrier layer is a film constituted by a material selected from the group consisting of TaN, Ta, TaNC, TaSiN, TIN, Ti, TiNC, and TiSiN.

4. The method according to claim 2, wherein the barrier layer is a film constituted by a material selected from the group consisting of RuTaN, RuTaNC, RuTiN, RuTiNC, RuN, and RuNC.

5. The method according to claim 1, wherein in step (i), the underlying alloy layer is formed as a copper diffusion barrier layer.

6. The method according to claim 5, wherein a wiring groove communicated with the interconnection hole is further formed above the interconnection hole in the interconnect dielectric layers, and in step (i), a surface of the wiring groove is also covered with the underlying alloy layer.

7. The method according to claim 5, wherein in step (ii), the copper or the copper compound is filled into the interconnection hole substantially or nearly in its entirety.

8. The method according to claim 5, further comprising filling copper by electrolytic plating into the remaining part of the interconnection hole which is not filled with the copper or the copper compound by CVD in step (ii), wherein a layer formed by CVD in step (ii) is used as a copper seed layer.

9. The method according to claim 6, further comprising filling copper by electrolytic plating into the remaining part of the interconnection hole which is not filled with the copper or the copper compound by CVD in step (ii) and the wiring groove, wherein the a layer formed by CVD in step (ii) is used as a copper seed layer.

10. The method according to claim 1, wherein the underlying alloy layer is a laminate comprised of the nitride film or the nitride-carbide film as a first layer and the carbide film as a second layer.

11. The method according to claim 10, wherein step (i) comprises controlling supply of a Ru precursor and supply of an M precursor to adjust an atomic ratio of Ru/(Ru+M) of the underlying layer at 0.6 to 0.9 for the first layer and then at 0.7 to 0.95 for the second layer.

12. The method according to claim 11, wherein the first layer is formed using a hydrogen-nitrogen plasma whereas the second layer is formed using a hydrogen plasma.

13. The method according to claim 1, wherein an atomic ratio of Ru/(Ru+M) of the underlying alloy layer is at about 0.6 to about 0.9.

14. The method according to claim 1, wherein step (i) comprises adjusting the atomic ratio of Ru/(Ru+M) of the underlying alloy layer by using a hydrogen plasma or a hydrogen-nitrogen plasma.

15. The method according to claim 1, wherein the Ru precursor is a β

-diketone-coordinated ruthenium compound.

16. The method according to claim 1, wherein the atomic layer deposition utilizes a plasma.

17. The method according to claim 13, wherein a proportion of Ru in the underlying alloy layer at a bottom of the connection hole is higher than that at a side wall of the connection hole or at an upper surface of the substrate.

18. The method according to claim 17, wherein the underlying alloy layer at the bottom contains less C and/or N than at the side wall or the upper surface.

19. The method according to claim 17, wherein the proportion of Ru is adjusted by applying bias voltage to the substrate.

20. The method according to claim 1, wherein step (i) comprises:

(I) conducting atomic deposition of M one time, the atomic deposition of M comprising supplying the M precursor and supplying a gas chemically reactive to the M precursor;

(II) after step (I), conducting atomic deposition of Ru two times, each atomic deposition of Ru comprising supplying the Ru precursor and supplying a reduction gas, and

(III) repeating steps (I) and (II) Z times, thereby forming a M-Ru alloy layer as the underlying alloy layer.

21. The method according to claim 20, wherein step (II) comprises applying radio-frequency power to the reduction gas to generate a plasma of the reduction gas.

22. The method according to claim 20, wherein the reduction gas is hydrogen gas or a mixed gas of hydrogen gas and nitrogen gas.

23. The method according to claim 21, wherein step (II) comprises applying negative potential to a heating support on which the substrate is placed.