Two step process for uniform across wafer deposition and void free filling on ruthenium coated wafers

• US 7,799,684 B1
• Filed: 03/05/2007
• Issued: 09/21/2010
• Est. Priority Date: 03/05/2007
• Status: Active Grant

• Current Assignee: Novellus Systems Incorporated (Lam Research Corporation)
• Original Assignee: Novellus Systems Incorporated (Lam Research Corporation)
• Inventors: Park, Seyang, Doubina, Natalia, Varadarajan, Seshasayee, Reid, Jonathan
• Primary Examiner(s): Blum; David S
• Application Number:
  US11/682,175
• Time in Patent Office: 1,296 Days
• Field of Search: 438/687, 257/E21.311, 257/E21.591
• US Class Current: 438/687
• CPC Class Codes: C25D 17/001 Apparatus specially adapted for electrolytic coating of wafers, e.g. semiconductors or solar cells
• CPC Class Codes: C25D 3/38 of copper
• CPC Class Codes: C25D 5/02 Electroplating of selected surface areas
• CPC Class Codes: C25D 5/10 Electroplating with more than one layer of the same or of different metals for bearings C25D7/10
• CPC Class Codes: C25D 5/18 Electroplating using modulated, pulsed or reversing current
• CPC Class Codes: C25D 5/619 Amorphous layers
• CPC Class Codes: C25D 7/123 Semiconductors first coated with a seed layer or a conductive layer
• CPC Class Codes: H01L 21/2885 using an external electrical current, i.e. electro-deposition
• CPC Class Codes: H01L 21/76864 Thermal treatment
• CPC Class Codes: H01L 21/76873 for electroplating
• CPC Class Codes: H01L 21/76877 Filling of holes, grooves or trenches, e.g. vias, with conductive material

Abstract

A two-step semiconductor electroplating process deposits copper onto wafers coated with a semi-noble metal in manner that is uniform across the wafer and free of voids. A plating bath nucleates copper uniformly and conformably at a high density in a very thin film. A second bath fills the features. A unique pulsed waveform enhances the nucleation density and reduces resistivity of the very thin film deposited in the nucleation operation. The process produces a thinner and conformal copper seed film than traditional PVD copper seed processes.

Claims

1. A semiconductor processing method for depositing copper comprising:

providing a semiconductor wafer having a semi-noble metal layer thereon;

depositing a seed layer of copper onto the metal layer using an electroplating process with an electrolyte comprising a copper salt and a copper complexing agent, wherein the electrolyte has a resistivity of at least about 200 ohms cm, thereby promoting a generally uniform deposition rate across a plating surface of the water.

2. The method of claim 1 further comprising:

depositing a bulk-layer of copper onto the seed layer of copper using an electroplating process employing a second electrolyte.

3. The method of claim 2, wherein the bulk-layer deposition process is performed under conditions that reduce the terminal effect.

4. The method of claim 3, wherein the bulk-layer deposition is performed by using a high resistivity virtual anode.

5. The method of claim 3, wherein the bulk-layer deposition is performed by using a sheath.

6. The method of claim 3, wherein the bulk-layer deposition is performed by using a plastic barrier with holes between the wafer and an anode.

7. The method of claim 3, wherein the bulk-layer deposition is performed by using one or more azimuthally asymmetric anodes.

8. The method of claim 3, wherein the bulk-layer deposition is performed by using baffles and/or plates to direct the flow of cations in the second electrolyte.

9. The method of claim 1, wherein the copper salt forms large anions in the electrolyte.

10. The method of claim 1, further comprising:

pretreating the wafer having a semi-noble metal layer by annealing the wafer and contacting the wafer with a forming gas.

11. The method of claim 10, wherein the wafer is heated to a temperature of between about 350 and 450 degrees Celsius to anneal the wafer.

12. The method of claim 10, wherein the wafer is heated for a period of between about 1 and 5 minutes.

13. The method of claim 1, further comprising:

spinning and drying the wafer after depositing the seed layer.

14. The method of claim 1, wherein the electrolyte resistivity is 200-5000 ohms cm.

15. The method of claim 1, wherein the electrolyte resistivity is 400-4000 ohms cm.

16. The method of claim 1, wherein the electrolyte resistivity is 1000-2000 ohms cm.

17. The method of claim 1, wherein the complexing agent is EDTA, citrate, pyrophosphate, oxalate, triethanolamine, dimercaptosuccinic acid, nitrilotriacetate, dimercaprol, desfuroxamine mesylate or combinations thereof.

18. The method of claim 1, wherein the copper salt is copper citrate, copper pyrophosphate, or copper oxalate.

19. The method of claim 1, wherein the electrolyte has a pH of about 2-6.

20. The method of claim 1, wherein the electrolyte comprises:

the complexing agent of EDTA at about 0.004-0.007M; and

the copper salt of copper citrate at about 0.004-0.007M.

21. The method of claim 1, wherein the electrolyte causes a copper plating reaction to occur at a cathodic potential of about 0.8-2.0 volts.

22. The method of claim 1, wherein the electrolyte causes a copper plating reaction to occur at a potential that is 200-1000 millivolts more cathodic than would occur in a conventional copper plating electrolyte.

23. The method of claim 1, wherein the electrolyte further comprises a wetting agent, wherein the wetting agent does not substantially impact the conductivity of the electrolyte.

24. The method of claim 23, wherein the wetting agent is polyethylene glycol, polypropylene glycol, or co-polymers of these chemicals.

25. The method of claim 23, wherein the concentration of the wetting agent is about 10-1000 mg/L.

26. The method of claim 23, wherein the concentration of the wetting agent is about 200-500 mg/L.

27. The method of claim 1, wherein the seed layer of copper deposited has a thickness of about 15-60 angstroms.

28. The method of claim 1, wherein features on the wafer after the seed layer copper deposition have an aspect-ratio less than about 15.

29. The method of claim 1, wherein features on the wafer after the seed layer copper deposition have an aspect-ratio less than about 10.

30. The method of claim 1, wherein depositing the seed layer comprises applying a current waveform, comprising:

a first step of applying a direct current for a first duration;

a second step of alternating forward and reverse current pulses for a second duration; and

a third step of applying a direct current for a third duration, wherein substantially all of the copper seed layer is deposited during the third step.

31. The method of claim 30, wherein the reverse current pulses strip off substantially all of the copper deposited during the forward current pulses.

32. The method of claim 31, wherein based on a 300 mm wafer, the forward current pulse is between about 0.6-0.9 amp for a period of about 700-1500 milliseconds, the reverse current pulse is about 0.2-0.5 amp for a period of about 400-600 milliseconds, and the second duration is about 8-15 seconds.

33. The method of claim 30, wherein the direct current of the first step is between about 0.6-1.0 amp for a period of about 0.5-2 seconds.

34. The method of claim 30, wherein the direct current of the third step is between about 0.6-1.0 amp, and the third duration is about 10-22 seconds to deposit a 30-70 angstrom seed layer.

35. The method of claim 1, wherein the semi-noble metal is ruthenium, palladium, rhodium, iridium, osmium, cobalt, or nickel.

36. The method of claim 1, wherein the semi-noble metal layer serves as at least a portion of a diffusion barrier.

38. The method of claim 37, wherein the wet deposition process is the seed layer depositing step of claim 1.

37. A semiconductor processing method for depositing copper comprising:

(a) providing a wafer;

(b) depositing copper onto the wafer using a wet deposition process;

(c) chemically etching the wafer so as to remove substantially all of the copper deposited;

(d) repeating steps (b) and (c) for at least 2 times; and

(e) depositing copper onto the wafer using an electroplating process until a desired thickness is reached.

39. The method of claim 37, wherein a chemical etchant used for chemically etching the wafer comprises peroxide and sulfuric acid, hydroiodic acid, glyoxylic acid, or a combination thereof.

40. The method of claim 37, wherein the wafer has a semi-noble metal layer thereon.